Leakage power consumption is a key issue in integrated circuit applications, and body bias adjustment technology is one of the most commonly used power consumption adjustment technologies. The traditional body bias adjustment circuit has problems such as small bias voltage range and multiple power supply voltages, which not only increases the cost of the entire system, but also limits the optimization effect of body bias adjustment technology. Based on the 22 nm FDSOI (Fully Depleted Silicon on Insulator) RVT (Regular Voltage Threshold) process, a wide-range body bias adjustment circuit suitable for 22 nm FDSOI RVT digital integrated circuits is proposed. This circuit has a programmable (0 V, ±2 V) wide voltage output range, can achieve 50 mV bias voltage resolution, and does not require additional power input. The test circuit was implemented based on the 22 nm FDSOI process. The simulation results show that the body bias adjustment circuit proposed in this design can reduce the standby leakage of the test circuit by 34% to 92% and has a wide performance tracking range.

Physical verification is a critical concern in chip manufacturing, ensuring chip yield. Detecting potential hotspots in the chip layout before actual manufacturing is a critical step, which ensures manufacturing feasibility and enhances production efficiency. Traditional hotspot detection techniques suffer from long detection cycles and high computational resource consumption, resulting in increased time costs throughout the production cycle and limited detection of hotspot patterns. Based on active learning techniques and visual state space models, this paper proposes a new hotspot detection model. A memory-based sampling strategy is employed for query evaluation to mitigate the impact of the imbalance between hotspot and non-hotspot data on the model. Furthermore, the resolution constraints of the CNN structure and the secondary complexity of the ViT network architecture are optimized, leading to linear complexity for the hotspot detector. Testing results on the ICCAD-2012 competition dataset show that the proposed hotspot detector significantly reduces the false positive rate, achieving a rate of only 1.47%, while the recall reaches an impressive 98.89%.

With the rapid proliferation of Internet of Things (IoT) technology, efficient data encryption in resource-constrained environments has become a critical issue hindering further development. Traditional encryption algorithms struggle to balance data confidentiality and integrity at low hardware resource consumption. In contrast, authenticated encryption techniques offer a robust security guarantee with minimal computational and memory overhead, making them an efficient solution for low-cost devices. This paper combines the flexibility of the RISC-V architecture with the efficiency of authenticated encryption algorithms, proposing a secure kernel that integrates authentication algorithms. This kernel tightly couples the general-purpose registers of the RISC-V core with dedicated computational modules, utilizing extended instructions for hardware acceleration to enhance the effective protection of data in IoT devices. Experimental results indicate that, compared with traditional coprocessor solutions, this design reduces logical resource consumption by approximately 60% while saving all additional register resources. Additionally, it provides about a 150-fold acceleration compared with pure software implementations. The proposed core module can deliver equivalent acceleration for other algorithms with similar underlying operators, demonstrating significant flexibility. This research offers an efficient and scalable encryption solution for modern IoT devices.