In the field of point cloud registration, the accuracy of the traditional Transformer method will decline in the case of low overlap due to the lack of geometric information perception and the loss of local details. In this research, a point cloud registration network based on multi-scale diffusion (MSD) model is proposed, which improves the robustness of the model through cooperative geometric coding and probability optimization strategy. Firstly, the network uses deformable convolution to construct feature pyramid, and combines with dynamic radius search technology to adapt to non-uniform distribution of point cloud data, so as to enhance the modeling ability of local surface continuity. Secondly, the triple geometry embedding mechanism is fused, and the hierarchical moving window attention mode is used to realize the effective coordination of local and global features. Finally, the transformation matrix is iteratively optimized in the double stochastic matrix space, and the Sinkhorn constraint is introduced to improve the stability. The experimental results show that the recall rate of MSD point cloud registration network on 3DMatch and 3DLoMatch datasets is significantly higher than other existing methods, which proves the superiority of this method. This study shows that by combining the multi-scale window attention mechanism and diffusion model, the matching accuracy and robustness in the point cloud registration task can be effectively improved.

Leakage power consumption is a key issue in integrated circuit applications, and body bias adjustment technology is one of the most commonly used power consumption adjustment technologies. The traditional body bias adjustment circuit has problems such as small bias voltage range and multiple power supply voltages, which not only increases the cost of the entire system, but also limits the optimization effect of body bias adjustment technology. Based on the 22 nm FDSOI (Fully Depleted Silicon on Insulator) RVT (Regular Voltage Threshold) process, a wide-range body bias adjustment circuit suitable for 22 nm FDSOI RVT digital integrated circuits is proposed. This circuit has a programmable (0 V, ±2 V) wide voltage output range, can achieve 50 mV bias voltage resolution, and does not require additional power input. The test circuit was implemented based on the 22 nm FDSOI process. The simulation results show that the body bias adjustment circuit proposed in this design can reduce the standby leakage of the test circuit by 34% to 92% and has a wide performance tracking range.

With the rapid proliferation of Internet of Things (IoT) technology, efficient data encryption in resource-constrained environments has become a critical issue hindering further development. Traditional encryption algorithms struggle to balance data confidentiality and integrity at low hardware resource consumption. In contrast, authenticated encryption techniques offer a robust security guarantee with minimal computational and memory overhead, making them an efficient solution for low-cost devices. This paper combines the flexibility of the RISC-V architecture with the efficiency of authenticated encryption algorithms, proposing a secure kernel that integrates authentication algorithms. This kernel tightly couples the general-purpose registers of the RISC-V core with dedicated computational modules, utilizing extended instructions for hardware acceleration to enhance the effective protection of data in IoT devices. Experimental results indicate that, compared with traditional coprocessor solutions, this design reduces logical resource consumption by approximately 60% while saving all additional register resources. Additionally, it provides about a 150-fold acceleration compared with pure software implementations. The proposed core module can deliver equivalent acceleration for other algorithms with similar underlying operators, demonstrating significant flexibility. This research offers an efficient and scalable encryption solution for modern IoT devices.