A Design of Tightly Coupled Chip for Authentication Encryption Based on RISC-V Processor

With the rapid proliferation of Internet of Things (IoT) technology, efficient data encryption in resource-constrained environments has become a critical issue hindering further development. Traditional encryption algorithms struggle to balance data confidentiality and integrity at low hardware resource consumption. In contrast, authenticated encryption techniques offer a robust security guarantee with minimal computational and memory overhead, making them an efficient solution for low-cost devices. This paper combines the flexibility of the RISC-V architecture with the efficiency of authenticated encryption algorithms, proposing a secure kernel that integrates authentication algorithms. This kernel tightly couples the general-purpose registers of the RISC-V core with dedicated computational modules, utilizing extended instructions for hardware acceleration to enhance the effective protection of data in IoT devices. Experimental results indicate that, compared with traditional coprocessor solutions, this design reduces logical resource consumption by approximately 60% while saving all additional register resources. Additionally, it provides about a 150-fold acceleration compared with pure software implementations. The proposed core module can deliver equivalent acceleration for other algorithms with similar underlying operators, demonstrating significant flexibility. This research offers an efficient and scalable encryption solution for modern IoT devices.