This study presents a column-level Analog-to-Digital Converter (ADC) designed specifically for Complementary Metal Oxide Semiconductor (CMOS) image sensors. It is characterized by a two-phase fully parallel architecture combined with Time-to-Digital Conversion (TDC) technology, resulting in high-speed performance. After the coarse-to-fine conversion process is completed, the output of the comparator is restricted by the clock signal. This results in the generation of a time difference value during the last clock cycle of the conversion. TDC is used to convert the difference into the corresponding numerical code and compare it with the ADC conversion results presented in this article. While realizing high-precision Analog-to-Digital (A/D) conversion, the conversion speed of ADCs has greatly improved. The circuit proposed in this article is developed and validated based on 55 nm CMOS technology. In a design environment, the analog voltage is set at 3.3 V, the digital voltage at 1.2 V, and the input signal range at 0−1.5 V. The entire system operates at a clock speed of 100 MHz. In this instance, the paper presents a 12-bit ADC that achieves an Integral Non-Linearity (INL) of +1.47/−1.74 Least Significant Bit (LSB), a Differential Non-Linearity (DNL) of +0.8/−0.8 LSB, and a Signal-to-Noise and Distortion Ratio (SNDR) of 68.272 dB. The ADC main architecture designed in this paper adopts a fully parallel design that is not limited to a fixed design accuracy. It achieves a high parallel time multiplexing rate of up to 100% through an adaptive time multiplexing mechanism. Additionally, the ADC architecture includes a 3-bit TDC, enhancing the efficiency of the A/D conversion process. The column ADC circuit presents an efficient ADC design solution that is well-suited for high frame rates and large-area array CMOS image sensors.

Aiming at the problem of the non-uniformity of the ramp signal in the super-large array CMOS (complementary metal-oxide semiconductor) image sensors, a ramp uniformity correction method for CMOS image sensors is proposed in this paper. Based on the error storage technique, the ramp non-uniformity error is stored. And the input ramp signal of each column is shifted by level-shifting technique to eliminate the ramp non-uniformity error. Based on the 55 nm-1P4M CMOS process, this paper has completed the detailed circuit design and comprehensive simulation verification of the proposed method. Under the design conditions that the voltage range of the ramp signal is 1.4 V, the slope of the ramp signal is 71.908 V/ms, the number of pixels is 8192 (H) × 8192 (V), and a single pixel size is 10 μm, the correction method proposed in this paper reduces the ramp non-uniformity error from 7.89 mV to 36 μV. The differential non-linearity of the ramp signal is +0.0013/−0.004 LSB and the integral non-linearity is +0.045/−0.021 LSB. The ramp uniformity correction method proposed in this paper reduces the ramp non-uniformity error by 99.54% on the basis of ensuring the high linearity of the ramp signal, without significantly increasing the chip area and without introducing additional power consumption. The column fixed-pattern noise is reduced from 1.9% to 0.01%. It provides theoretical support for the design of high-precision CMOS image sensors.

Bipolar transistor base current leakage and a drop in current gain will occur in bandgap reference circuits exposed to total dose radiation. This will cause the output voltage of the bandgap reference to move and its dependability to decline. To address the issues of high cost, large layout area, and low universality that traditional total dose reinforcement methods for bandgap references based on process, layout, and device can bring, this method is suggested. An on-chip total dose real-time monitoring and adaptive compensation method is proposed to realize circuit-level total dose reinforcement and improve the radiation resistance of bandgap references. Based on the 0.18 μm BCD (Bipolar-CMOS-DMOS) process, specific circuit design, back-end physical implementation and comprehensive verification of the proposed method are carried out. Under radiation conditions of 100−300 krad (Si) under various process angles, the results demonstrate that the output voltage offset of the bandgap reference is improved from 3.4−18.5 mV voltage offset (100−300 krad) prior to reinforcement to the maximum offset voltage following reinforcement, which is 1 mV (100−300 krad). This provides a new method for designing irradiation-resistant reinforcement of bandgap references at the circuit and system levels.

Infrared image sensing technology has received widespread attention due to its advantages of not being affected by the environment, good target recognition, and strong anti-interference ability. However, with the improvement of the integration of the infrared focal plane, the constraints among the dynamic range, noise, and full well capacity of the photoelectric system are particularly prominent. Therefore, in order to solve the contradiction between noise in low light and full well capacity in strong light, in the 5T infrared pixel circuit, the relationship between the capacitance value and voltage of the inverse MOS capacitor in a specific voltage interval was used to automatically change the integral capacitance of the infrared image sensor from 6.5 fF to 37.5 fF, and a highly dynamic pixel structure based on adaptive integral capacitance was proposed. Based on 55 nm CMOS process technology, the performance parameters of an infrared sensor with a 12 288 × 12 288 pixel scale were studied. The research results show that a small-size pixel of 5.5 µm × 5.5 µm has a large full well capacity of 1.31 Me⁻, and a variable conversion gain. The noise is less than 0.43 e⁻, and the dynamic range is more than 130 dB.

DC-DC converter in the total dose radiation environment will mainly bring the output voltage drift, linear adjustment rate load adjustment rate decline and other effects so that the output stability performance of the circuit deteriorates. In order to address the issues with the conventional total ionizing dose effect hardening method that stem from process and layout, including high cost, large layout area, and poor universality, this paper suggests a total ionizing dose effect hardening design method with parallel monitoring and hardening. This method can accomplish total ionizing dose effect hardening at the circuit level without the need for a process. The anti-total dose capability of the Buck-Boost converter is improved. The circuit design and physical implementation of the proposed method are verified based on the 0.18 μm BCD process. According to the findings, with a dosage of 2000 Gy (Si), it is possible to enhance the output voltage shift rate from 0.0663% to 0.0074% and compensate the system gain drop rate from 19.26% to 6.65%. The load adjustment rate and linear adjustment rate are reduced by 2.15%/A and 0.0389%/V, respectively, which provides a new idea for the design of total ionizing dose effect hardening at the circuit and system level.