This study presents a column-level Analog-to-Digital Converter (ADC) designed specifically for Complementary Metal Oxide Semiconductor (CMOS) image sensors. It is characterized by a two-phase fully parallel architecture combined with Time-to-Digital Conversion (TDC) technology, resulting in high-speed performance. After the coarse-to-fine conversion process is completed, the output of the comparator is restricted by the clock signal. This results in the generation of a time difference value during the last clock cycle of the conversion. TDC is used to convert the difference into the corresponding numerical code and compare it with the ADC conversion results presented in this article. While realizing high-precision Analog-to-Digital (A/D) conversion, the conversion speed of ADCs has greatly improved. The circuit proposed in this article is developed and validated based on 55 nm CMOS technology. In a design environment, the analog voltage is set at 3.3 V, the digital voltage at 1.2 V, and the input signal range at 0−1.5 V. The entire system operates at a clock speed of 100 MHz. In this instance, the paper presents a 12-bit ADC that achieves an Integral Non-Linearity (INL) of +1.47/−1.74 Least Significant Bit (LSB), a Differential Non-Linearity (DNL) of +0.8/−0.8 LSB, and a Signal-to-Noise and Distortion Ratio (SNDR) of 68.272 dB. The ADC main architecture designed in this paper adopts a fully parallel design that is not limited to a fixed design accuracy. It achieves a high parallel time multiplexing rate of up to 100% through an adaptive time multiplexing mechanism. Additionally, the ADC architecture includes a 3-bit TDC, enhancing the efficiency of the A/D conversion process. The column ADC circuit presents an efficient ADC design solution that is well-suited for high frame rates and large-area array CMOS image sensors.

Aiming at the problem of the non-uniformity of the ramp signal in the super-large array CMOS (complementary metal-oxide semiconductor) image sensors, a ramp uniformity correction method for CMOS image sensors is proposed in this paper. Based on the error storage technique, the ramp non-uniformity error is stored. And the input ramp signal of each column is shifted by level-shifting technique to eliminate the ramp non-uniformity error. Based on the 55 nm-1P4M CMOS process, this paper has completed the detailed circuit design and comprehensive simulation verification of the proposed method. Under the design conditions that the voltage range of the ramp signal is 1.4 V, the slope of the ramp signal is 71.908 V/ms, the number of pixels is 8192 (H) × 8192 (V), and a single pixel size is 10 μm, the correction method proposed in this paper reduces the ramp non-uniformity error from 7.89 mV to 36 μV. The differential non-linearity of the ramp signal is +0.0013/−0.004 LSB and the integral non-linearity is +0.045/−0.021 LSB. The ramp uniformity correction method proposed in this paper reduces the ramp non-uniformity error by 99.54% on the basis of ensuring the high linearity of the ramp signal, without significantly increasing the chip area and without introducing additional power consumption. The column fixed-pattern noise is reduced from 1.9% to 0.01%. It provides theoretical support for the design of high-precision CMOS image sensors.