Flexible integrated electronic technology enables the next generation of more flexible, freer, lighter, and smaller intelligent hardware, providing information sensing and edge computing capabilities for applications such as embodied intelligence, healthcare, and industrial Internet of Things. By thinning and integrating diverse chips onto a thin‐film polymer substrate, these flexible integrated devices retain advantages of semiconductor devices, including high integration density, low power consumption, and mature front‐end processes, without altering the fundamental device structures and materials. Although the electrical performance of ultra‐thin chips remains essentially unchanged after flexible packaging, the mechanical reliability during repeated bending deformation has been a critical concern due to the significant property mismatch between silicon and polymer materials, which may cause silicon fracture, interfacial failure, and eventual device failure. This study investigates and evaluates the fatigue lifetime of 20‐μm‐thick chips under repeated bending deformation with various radii of curvature. Through systematic experiments, the typical failure phenomena evolution is observed, finding three types of failure modes including metal pad wearing, metal stress migration, and gold wire break. The underlying failure mechanisms have been analyzed and explained by micro‐scale characterization. Finally, temperature effect on the fatigue lifetime has been explored trying to throw light on heating‐based accelerated fatigue life assessment method for the flexible chips. Hopefully, this work can provide essential support for the design to large‐scale application of flexible integrated devices in the widespread intelligent hardware products.

Ultra-thin and flexible silicon chips are pivotal for high-performance conformal electronics. Backside grinding reduces chip thickness below 50 μm, enabling mass production of ultra-thin flexible chips in a low-cost way, yet the resulting defects and residual stress on the backside may propagate to the frontside circuits degrading the electric performance, especially for the critical-thickness devices. Here, commercial pulse-width modulation (PWM) chip wafers (involving tens of thousands of dies) based on bipolar transistors have been thinned to the thickness of ~ 20 μm by mechanical grinding with different parameters. Experimental results reveal a thickness-dependent bifurcated failure mechanism: Short-circuit current decays progressively with thickness reduction, while leakage current exhibits a catastrophic surge below the critical thickness (~ 18 μm). This work reveals a dual degradation mechanism in ultrathin ICs: Mechanical grinding not only amplifies substrate parasitic coupling via geometric thinning but also generates stress fields that induces dislocation rearrangement-aggregation cascades, ultimately dictating electrical failure modes. Chemical mechanical polishing (CMP) and reactive ion etching (RIE) have been deployed to inhibit leakage current surges by removing grinding-induced damaged layers and relieving interfacial residual stress, which collectively validate the stress-defect interaction as the governing mechanism of electrical failure in ultra-thin chips (UTCs). Hopefully, this study can throw light on the impact of mechanical grinding thinning on the electrical performance of ultra-thin chips paving the way to the wide applications of high-performance flexible electronics in the future.