Wafer-scale flexible silicon transistor: The role of thinning induced stress and defects on device performance

Ultra-thin and flexible silicon chips are pivotal for high-performance conformal electronics. Backside grinding reduces chip thickness below 50 μm, enabling mass production of ultra-thin flexible chips in a low-cost way, yet the resulting defects and residual stress on the backside may propagate to the frontside circuits degrading the electric performance, especially for the critical-thickness devices. Here, commercial pulse-width modulation (PWM) chip wafers (involving tens of thousands of dies) based on bipolar transistors have been thinned to the thickness of ~ 20 μm by mechanical grinding with different parameters. Experimental results reveal a thickness-dependent bifurcated failure mechanism: Short-circuit current decays progressively with thickness reduction, while leakage current exhibits a catastrophic surge below the critical thickness (~ 18 μm). This work reveals a dual degradation mechanism in ultrathin ICs: Mechanical grinding not only amplifies substrate parasitic coupling via geometric thinning but also generates stress fields that induces dislocation rearrangement-aggregation cascades, ultimately dictating electrical failure modes. Chemical mechanical polishing (CMP) and reactive ion etching (RIE) have been deployed to inhibit leakage current surges by removing grinding-induced damaged layers and relieving interfacial residual stress, which collectively validate the stress-defect interaction as the governing mechanism of electrical failure in ultra-thin chips (UTCs). Hopefully, this study can throw light on the impact of mechanical grinding thinning on the electrical performance of ultra-thin chips paving the way to the wide applications of high-performance flexible electronics in the future.