Based on a 40 nm CMOS process, a high-gain low noise amplifier (LNA) chip was designed. The topology architecture of the chip adopted transformer input matching technology and positive feedback same-phase amplification technology to improve the input matching degree and gain. By introducing an active biasing network and a transformer matching network into the input stage of the traditional common-source common-gate structure, the chip can not only work stably at room temperature, but also shows excellent performance within the temperature range of −40 ℃ to 125 ℃ in simulation. Therefore, this design can be used for transceiver receiving ports in millimeter wave frequency bands under different temperature environments, and has certain temperature stability characteristics. The chip’s layout size is 0.383 mm×0.694 mm. The post-layout simulation results show that the LNA achieves a noise figure of less than 4.96 dB, a maximum gain of 18.11 dB, an input return loss of less than −16.08 dB, and an output return loss of less than −11.54 dB within the working frequency range of 24~27 GHz at room temperature. In addition, the LNA design has excellent performance indicators such as an input P_1dB of −20.36 dBm and a DC power dissipation of 12.8 mW.

To address the urgent demand for high-efficiency, high-linearity, and broadband performance in S-band (2~4 GHz) radio frequency power amplifiers (PAs) for 5G Sub-6 GHz communication systems, an innovative design is proposed based on Gallium Arsenide Pseudomorphic High Electron Mobility Transistor (GaAs pHEMT) technology. Traditional silicon-based CMOS processes faced limitations in high-frequency scenarios due to breakdown voltage and parasitic effects, while Gallium Nitride (GaN) technology struggled with cost and integration challenges. The research focused on leveraging the potential of GaAs pHEMT technology to overcome efficiency, bandwidth, and harmonic suppression bottlenecks in S-band PAs and explored its integration in radio frequency front-end modules. The study employed a hybrid π-shaped harmonic matching network combined with reactance compensation technology. A single-stage topology integrated impedance transformation, harmonic suppression, and dynamic parasitic parameter compensation, resolving the limitations of traditional multi-stage LC networks (bandwidth <10%) and excessive area occupation. Off-chip discrete LC compensation modules were introduced to optimize high-frequency parasitic effects, and a two-stage cascaded architecture (driver stage and power stage) enhanced gain and power output. By precisely tuning gate (0.38 V/0.45 V) and drain (6 V) bias voltages, along with symmetric layout design and electromagnetic simulation optimization, nonlinear distortion and DC power consumption were significantly reduced. Experimental results demonstrate that the designed Class-E PA achieves a 15% fractional bandwidth in the 2.45~2.85 GHz range, with a second harmonic suppression ratio exceeding 20 dB (at 5.3 GHz) and optimized load impedance of 50 Ω. The measured power-added efficiency (PAE) reaches 56.4% at the center frequency of 2.65 GHz, with an output power of 26.2 dBm and a gain of 26 dB, outperforming existing solutions.