A Design of a 24-27 GHz Cascode High Gain Low Noise Amplifier

Based on a 40 nm CMOS process, a high-gain low noise amplifier (LNA) chip was designed. The topology architecture of the chip adopted transformer input matching technology and positive feedback same-phase amplification technology to improve the input matching degree and gain. By introducing an active biasing network and a transformer matching network into the input stage of the traditional common-source common-gate structure, the chip can not only work stably at room temperature, but also shows excellent performance within the temperature range of −40 ℃ to 125 ℃ in simulation. Therefore, this design can be used for transceiver receiving ports in millimeter wave frequency bands under different temperature environments, and has certain temperature stability characteristics. The chip’s layout size is 0.383 mm×0.694 mm. The post-layout simulation results show that the LNA achieves a noise figure of less than 4.96 dB, a maximum gain of 18.11 dB, an input return loss of less than −16.08 dB, and an output return loss of less than −11.54 dB within the working frequency range of 24~27 GHz at room temperature. In addition, the LNA design has excellent performance indicators such as an input P_1dB of −20.36 dBm and a DC power dissipation of 12.8 mW.