This paper presents a resolution reconfigurable two-step successive approximation register analog-to-digital (A/D) converter (ADC) with the pseudo-multiple sampling (PMS) and gain error calibration method for CMOS image sensors. The proposed ADC can be configured with 10-bit, 11-bit and 12-bit by adjusting the number of 10-bit A/D conversions, thereby satisfying various demands in different situations. The PMS method enables the attainment of high-resolution ADC results by summing the conversion outputs of several low-resolution ADCs, thereby reducing the number of unit capacitors and the area of the capacitor array. A compensation technique is proposed to expand the quantization range and improve the effective resolution of the proposed ADC. A calibration method suitable for bottom-plate sampling is proposed, which reduces the gain error between reference voltages. Simulated in a 55 nm process, the proposed ADC in the 12-bit mode achieves a differential nonlinearity of +0.47/−0.50 least significant bit (LSB) and an integral nonlinearity of +0.75/−0.84 LSB at a sampling frequency of 3.497×10⁵ per second with the calibration. The effective number of bits reaches 11.63 bits. The area occupied by a single ADC column is 39.5 µm×119.2 µm and the power consumption is 62.8 µW.

In computing-in-memory (CIM) chips, analogue computing is more efficient than traditional digital computing due to its low power consumption. As a critical unit in analogue computing, the weighted charge accumulation circuit (WCAC) is challenging to measure because of its complex test pattern and control timing. In order to solve these problems, two key performance metrics: linearity and error distribution, are analysed based on the characteristics of analogue computing architecture and data flow. Further, the design scheme of the test system is proposed, and the test pattern is designed according to target data sets to measure linearities and error distribution. The simulation and measurement results of linearity are 99.79% and 99.11%, respectively. For the error distribution, the mean value of the simulation is -0.06 mV, and the standard deviation is 1.54 mV. The measurement result indicates the same distribution trend as the simulation, with a mean value of 0.37 mV and a standard deviation of 2.07 mV. Overall, the circuit exhibits excellent linearity and calculation accuracy. Furthermore, to evaluate the reliability of the WCAC in network models, the measured error distribution metrics are abstracted into LeNet and AlexNet, respectively, and accuracy experiments are performed on MNIST and CIFAR-10. Experimental results reveal that the accuracies of LeNet on MNIST are reduced by 0.25% and 0.18%, when weight parameters are quantized to 4 bits and 8 bits. The accuracy of AlexNet on CIFAR-10 is reduced by 3.12%, when weight parameters are quantized to 8 bits.