Linearity and error distribution measurement of weighted charge accumulation circuit for computing-in-memory

In computing-in-memory (CIM) chips, analogue computing is more efficient than traditional digital computing due to its low power consumption. As a critical unit in analogue computing, the weighted charge accumulation circuit (WCAC) is challenging to measure because of its complex test pattern and control timing. In order to solve these problems, two key performance metrics: linearity and error distribution, are analysed based on the characteristics of analogue computing architecture and data flow. Further, the design scheme of the test system is proposed, and the test pattern is designed according to target data sets to measure linearities and error distribution. The simulation and measurement results of linearity are 99.79% and 99.11%, respectively. For the error distribution, the mean value of the simulation is -0.06 mV, and the standard deviation is 1.54 mV. The measurement result indicates the same distribution trend as the simulation, with a mean value of 0.37 mV and a standard deviation of 2.07 mV. Overall, the circuit exhibits excellent linearity and calculation accuracy. Furthermore, to evaluate the reliability of the WCAC in network models, the measured error distribution metrics are abstracted into LeNet and AlexNet, respectively, and accuracy experiments are performed on MNIST and CIFAR-10. Experimental results reveal that the accuracies of LeNet on MNIST are reduced by 0.25% and 0.18%, when weight parameters are quantized to 4 bits and 8 bits. The accuracy of AlexNet on CIFAR-10 is reduced by 3.12%, when weight parameters are quantized to 8 bits.