Considering that the hardware implementation of the normalized minimum sum (NMS) decoding algorithm for low-density parity-check (LDPC) code is difficult due to the uncertainty of scale factor, an NMS decoding algorithm with variable scale factor is proposed for the near-earth space LDPC codes (8177,7154) in the consultative committee for space data systems (CCSDS) standard. The shift characteristics of field programmable gate array (FPGA) is used to optimize the quantization data of check nodes, and finally the function of LDPC decoder is realized. The simulation and experimental results show that the designed FPGA-based LDPC decoder adopts the scaling factor in the NMS decoding algorithm to improve the decoding performance, simplify the hardware structure, accelerate the convergence speed and improve the error correction ability.

In order to solve the low-power design of reed-solomon (RS) code, it is carried out from different design levels such as system architecture, RTL level and gate level, etc. And it is practiced in application specific integrated circuit (ASIC) design. The back-end IC design is combined to study the chip that can realize the RS coding function. At the system architecture level, the multiplication operation of Galois field in the RS coding algorithm has problems such as large amount of data operation and high-power consumption in hardware implementation. A method based on a multiplier factor matrix is proposed to optimize the RS coding algorithm. The data operation is reduced by converting multiplication operation to subtraction operation, so as to reduce power consumption. At the RTL level and gate level, the logic synthesis and back-end implementation are constrained to implement the low power design, and the overall power consumption can be reduced by about 60%. The problem of high-power consumption of IC chip is solved, which leads to the decline of chip performance, affects the normal operation of the chip and provides a new direction for the integrated circuit process.