An FPGA-based LDPC decoder with optimized scale factor of NMS decoding algorithm

Considering that the hardware implementation of the normalized minimum sum (NMS) decoding algorithm for low-density parity-check (LDPC) code is difficult due to the uncertainty of scale factor, an NMS decoding algorithm with variable scale factor is proposed for the near-earth space LDPC codes (8177,7154) in the consultative committee for space data systems (CCSDS) standard. The shift characteristics of field programmable gate array (FPGA) is used to optimize the quantization data of check nodes, and finally the function of LDPC decoder is realized. The simulation and experimental results show that the designed FPGA-based LDPC decoder adopts the scaling factor in the NMS decoding algorithm to improve the decoding performance, simplify the hardware structure, accelerate the convergence speed and improve the error correction ability.