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Design and analysis of a low-power HMAC hardware architecture
Journal of Measurement Science and Instrumentation 2026, 17(3): 435-445
Published: 01 September 2026
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Hash-based message authentication code (HMAC) modules often operate for extended periods in power-constrained embedded security terminals and edge-trusted computing devices, easily creating a significant energy bottleneck issues. To address this challenge, we propose a module-level collaborative low-power hardware architecture for HMAC-SHA-256. Exploiting the phased computational characteristics of the HMAC algorithm, a top-level finite state machine (FSM) coordinates clock gating, datapath gating, and power gating to selectively disable inactive modules across different computation stages, thereby reducing clock activity, redundant switching in combinational logic, and leakage power. Gate-level simulations based on an SMIC 55 nm technology at 100 MHz demonstrate that, without degrading operating frequency, the proposed architecture reduces total power consumption from 40.830 mW to 19.902 mW (a 51.3% reduction), while achieving an approximately 14.8% reduction in logic-synthesis-equivalent area. These results indicate that the proposed approach effectively minimizes task energy under strict performance constraints and provides a reusable low-power design methodology for HMAC hardware implementations in resource-constrained environments.

Open Access Issue
FPGA-based design of laser gyro signal acquisition circuit
Journal of Measurement Science and Instrumentation 2025, 16(1): 107-118
Published: 01 March 2025
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With the continuous evolution of electronic technology, field-programmable gate array (FPGA) has demonstrated significant advantages in the realm of signal acquisition and processing, and signal acquisition plays a pivotal role in the practical applications of laser gyros. By analysis of the output signals from a laser gyro and an accelerometer, this paper presents a circuit design for signal acquisition of the laser gyro based on domestic devices. The design incorporates a finite impulse response (FIR) filter to process the gyro signal and employs a small-volume, impact-resistant quartz flexible accelerometer for signal aquisition. Simulation results demonstrate that the errors in X, Y, and Z axes fall within acceptable ranges while meeting filtering requirements. The use of FPGA for signal acquisition and preprocessing enhances configuration flexibility, which provides an idea and method for optimizing performance and processing signals in laser gyro applications.

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