Design and analysis of a low-power HMAC hardware architecture

Hash-based message authentication code (HMAC) modules often operate for extended periods in power-constrained embedded security terminals and edge-trusted computing devices, easily creating a significant energy bottleneck issues. To address this challenge, we propose a module-level collaborative low-power hardware architecture for HMAC-SHA-256. Exploiting the phased computational characteristics of the HMAC algorithm, a top-level finite state machine (FSM) coordinates clock gating, datapath gating, and power gating to selectively disable inactive modules across different computation stages, thereby reducing clock activity, redundant switching in combinational logic, and leakage power. Gate-level simulations based on an SMIC 55 nm technology at 100 MHz demonstrate that, without degrading operating frequency, the proposed architecture reduces total power consumption from 40.830 mW to 19.902 mW (a 51.3% reduction), while achieving an approximately 14.8% reduction in logic-synthesis-equivalent area. These results indicate that the proposed approach effectively minimizes task energy under strict performance constraints and provides a reusable low-power design methodology for HMAC hardware implementations in resource-constrained environments.