This study used adaptive iterative pruning and search-based bias-free quantization approaches to minimize model complexity and storage requirements while preserving accuracy in response to the deployment and execution problems of Swin Transformer models in resource-constrained situations. Initially, Adaptive iterative pruning dynamically eliminated non-essential weights, reducing storage and computational demands. Subsequently, Search-based bias-Free quantization optimized the storage of weights and activation values, further minimizing model size with minimal accuracy loss. In terms of hardware design, an accelerator architecture tailored for Swin Transformer models was put out, improving data processing efficiency and speed via hardware-level adjustments. Experimental results indicated that after applying pruning and quantization, the model's size reduced to 14.4% of its original, achieving a Top-1 accuracy of 77.4% on the ImageNet-1K dataset.

As the pre-order step of convolutional neural network (CNN) computing, image preprocessing is indispensable but time-consuming. To accelerate image preprocessing, a method based on RISC-V vector extension was proposed to accelerate eleven image preprocessing algorithms such as gray scale processing, standardization, and Gaussian filtering. Firstly, eleven image preprocessing algorithms were classified into four categories according to the computing mode, and acceleration schemes for the preprocessing algorithms were designed based on RISC-V vector extension. In order to further improve the performance, six customized vector instructions were added. The customized instructions were implemented by modifying the compiler and designing the hardware module. Finally, a field programmable gate array (FPGA) was used for testing, and the impact of vector processor configuration on performance and resource consumption was analyzed. The results showed that the proposed method achieves 3.13–9.97 times speedup compared with scalar processors, which effectively solves the performance bottleneck problem of image preprocessing in deep learning.

For data flow errors caused by fault attacks during processor operation, this paper designed a configurable fault injection detection method based on RISC-V processor microarchitecture. Based on the RISC-V instruction set architecture, this method took advantage of its expandability to add custom arithmetic logic instructions with mode configuration and control and state registers and realized the arithmetic logic operation and fault detection simultaneously by the combination of hardware and software. At the software level, configuration information was written to the customized control and state register by register access instructions to configure the fault detection modes of the customized instructions, including information and temporal redundancy modes and their parameters. At the hardware level, a RISC-V processor microarchitecture supporting configurable fault injection detection was implemented. Finally, the simulator command was used to simulate the fault injection, and the functional correctness and fault injection detection capability of the extended RISC-V processor were verified. The experimental results show that compared to the single information redundancy method, when the information redundancy mode and temporal redundancy mode are applied with the same frequency, the proposed configurable method improves the average fault detection rate by 13.34% with an average resource overhead of 4.4%. Compared to the single temporal redundancy method, it reduces the average time overhead by 8.24% with a 13.33% decrease in fault detection rate. The proposed configurable method can achieve a compromise between fault detection rate and time overhead and be applied in application scenarios with different security and performance requirements.