Configurable fault injection detection method for RISC-V based on instruction extension

For data flow errors caused by fault attacks during processor operation, this paper designed a configurable fault injection detection method based on RISC-V processor microarchitecture. Based on the RISC-V instruction set architecture, this method took advantage of its expandability to add custom arithmetic logic instructions with mode configuration and control and state registers and realized the arithmetic logic operation and fault detection simultaneously by the combination of hardware and software. At the software level, configuration information was written to the customized control and state register by register access instructions to configure the fault detection modes of the customized instructions, including information and temporal redundancy modes and their parameters. At the hardware level, a RISC-V processor microarchitecture supporting configurable fault injection detection was implemented. Finally, the simulator command was used to simulate the fault injection, and the functional correctness and fault injection detection capability of the extended RISC-V processor were verified. The experimental results show that compared to the single information redundancy method, when the information redundancy mode and temporal redundancy mode are applied with the same frequency, the proposed configurable method improves the average fault detection rate by 13.34% with an average resource overhead of 4.4%. Compared to the single temporal redundancy method, it reduces the average time overhead by 8.24% with a 13.33% decrease in fault detection rate. The proposed configurable method can achieve a compromise between fault detection rate and time overhead and be applied in application scenarios with different security and performance requirements.