With the rapid expansion of genomic sequencing data over the years, the costs associated with storage, transmission, and bandwidth are becoming the primary bottlenecks in genomic research and applications. Data compression is widely used to alleviate this burden, provided it achieves a sufficiently high compression ratio and fast compression speed. MPEG-G is a genome-specific compression standard that offers a higher compression ratio than general-purpose compression tools (4.3x), however, at the cost of performance reduction (5x). Following common strategies in compression acceleration, we design to the best of our knowledge, the first hardware accelerator for the MPEG-G genomic data compression pipeline utilizing in-SRAM (Static Random-Access Memory) computing, referred to as iSCoder. We identify and analyze MatchC (Match Coding) and LutC (Lut Coding) as two bottleneck algorithms within this pipeline, propose two optimized in-SRAM algorithms, and design a unified hardware architecture for these algorithms, considering the characteristics of genomic data. Compared with 72-core Intel processors operating at 3.0 GHz, experimental results demonstrate that iSCoder achieves an average speedup of 131x for MatchC and 191x for LutC.
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As one typical AI-for-Science application, machine learning interatomic potentials (MLIPs) have revolutionized the representation of potential energy surfaces. MLIPs can be categorized into specialized MLIPs, which prioritize high accuracy for specific systems, and pretrained MLIPs, which emphasize generalizability across chemical spaces. Specialized MLIPs and pretrained MLIPs differ in the dataset to be trained, model capability (parameters), the training workflow, and the workload in molecular dynamics. We review different high-performance computing (HPC) optimization techniques for training and inference that specialized MLIPs and pretrained MLIPs tend to prefer. For example, from the perspective of the training dataset, we investigate the load balance strategies, which are critical for pretrained MLIPs to enhance scalability. From the perspective of model parameters, we indicate that specialized MLIPs can benefit from curvature-aware optimization algorithms given their moderate model size. We remark that advances in HPC are not merely engineering improvements but play a key role in faster iteration of MLIPs, broader applicability, and sustained progress in MLIP development.
Base-calling is an essential step in the analysis of third-generation genome data. Many previous hardware efforts aimed at enhancing processing in the workflow. However, an order of magnitude throughput gap still exists. In this paper, we propose FuHsi to improve the end-to-end throughput of the base-calling process. FuHsi is an in-cache accelerator that only introduces three components to the traditional CPUs in the sequencer. We propose FuHsi Cache, which offloads the bottleneck operations to cache arithmetic. Specifically, we accelerate beam search, string conversion, and MAC (multiply-accumulate) using algorithm/hardware co-design. We also introduce FuHsi APIs and FuHsi Controller to provide coarse-grained control for FuHsi Cache. Experimental results show that FuHsi can achieve 45.7x, 113.1x, and 100x throughput per watt speedup compared with an NVIDIA Jetson baseline, an NVIDIA A100 GPU baseline, and the Helix accelerator, respectively. FuHsi can provide base-calling requests for up to 15 ONT sequencers simultaneously.
The escalating demand on batched deep learning inference requires concurrent deployment of multiple deep neural network (DNN) models on a shared accelerator, thereby enabling spatial multiplexing to enhance resource utilization. Spatial multiplexing for co-locating multiple model services on the same accelerator increases the complexity of scheduling within a cluster. The meticulous collaborative optimization of model co-location combinations and resource allocation in a cluster creates an extensive configuration space for scheduling. In this paper, we present
The growing demand for semiconductor devices simulation poses a big challenge for large-scale electronic structure calculations. Among various methods, the linearly scaling three-dimensional fragment (LS3DF) method exhibits excellent scalability in large-scale simulations. Based on algorithmic and system-level optimizations, we propose a highly scalable and highly efficient implementation of LS3DF on the Sugon supercomputer, a domestic supercomputer equipped with deep computing units. In terms of algorithmic optimizations, the original all-band conjugate gradient algorithm is refined to achieve faster convergence, and mixed precision computing is adopted to increase overall efficiency. In terms of system-level optimizations, the original two-layer parallel structure is replaced by a coarse-grained parallel method. Optimization strategies such as multi-stream, kernel fusion, and redundant computation removal are proposed to increase further utilization of the computational power provided by the heterogeneous machines. As a result, our optimized LS3DF can scale to a 10-million silicon atoms system, attaining a peak performance of 34.8 PFLOPS (21.2% of the peak). All the improvements can be adapted to the next-generation supercomputers for larger simulations.
Genomic sequence alignment is the most critical and time-consuming step in genomic analysis. Alignment algorithms generally follow a seed-and-extend model. Acceleration of the extension phase for sequence alignment has been well explored in computing-centric architectures on field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), and graphics processing unit (GPU) (e.g., the Smith-Waterman algorithm). Compared with the extension phase, the seeding phase is more critical and essential. However, the seeding phase is bounded by memory, i.e., fine-grained random memory access and limited parallelism on conventional system. In this paper, we argue that the processing-in-memory (PIM) concept could be a viable solution to address these problems. This paper describes “PIM-Align”—application-driven near-data processing architecture for sequence alignment. In order to achieve memory-capacity proportional performance by taking advantage of 3D-stacked dynamic random access memory (DRAM) technology, we propose a lightweight message mechanism between different memory partitions, and a specialized hardware prefetcher for memory access patterns of sequence alignment. Our evaluation shows that the proposed architecture can achieve 20x and 1820x speedup when compared with the best available ASIC implementation and the software running on 32-thread CPU, respectively.
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