Base-calling is an essential step in the analysis of third-generation genome data. Many previous hardware efforts aimed at enhancing processing in the workflow. However, an order of magnitude throughput gap still exists. In this paper, we propose FuHsi to improve the end-to-end throughput of the base-calling process. FuHsi is an in-cache accelerator that only introduces three components to the traditional CPUs in the sequencer. We propose FuHsi Cache, which offloads the bottleneck operations to cache arithmetic. Specifically, we accelerate beam search, string conversion, and MAC (multiply-accumulate) using algorithm/hardware co-design. We also introduce FuHsi APIs and FuHsi Controller to provide coarse-grained control for FuHsi Cache. Experimental results show that FuHsi can achieve 45.7x, 113.1x, and 100x throughput per watt speedup compared with an NVIDIA Jetson baseline, an NVIDIA A100 GPU baseline, and the Helix accelerator, respectively. FuHsi can provide base-calling requests for up to 15 ONT sequencers simultaneously.

Genomic sequence alignment is the most critical and time-consuming step in genomic analysis. Alignment algorithms generally follow a seed-and-extend model. Acceleration of the extension phase for sequence alignment has been well explored in computing-centric architectures on field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), and graphics processing unit (GPU) (e.g., the Smith-Waterman algorithm). Compared with the extension phase, the seeding phase is more critical and essential. However, the seeding phase is bounded by memory, i.e., fine-grained random memory access and limited parallelism on conventional system. In this paper, we argue that the processing-in-memory (PIM) concept could be a viable solution to address these problems. This paper describes “PIM-Align”—application-driven near-data processing architecture for sequence alignment. In order to achieve memory-capacity proportional performance by taking advantage of 3D-stacked dynamic random access memory (DRAM) technology, we propose a lightweight message mechanism between different memory partitions, and a specialized hardware prefetcher for memory access patterns of sequence alignment. Our evaluation shows that the proposed architecture can achieve 20x and 1820x speedup when compared with the best available ASIC implementation and the software running on 32-thread CPU, respectively.