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Research Article Issue
Device performance limit of monolayer SnSe2 MOSFET
Nano Research 2022, 15 (3): 2522-2530
Published: 02 September 2021
Downloads:57

Two-dimensional (2D) semiconductors are attractive channels to shrink the scale of field-effect transistors (FETs), and among which the anisotropic one is more advantageous for a higher on-state current (Ion). Monolayer (ML) SnSe2, as an abundant, economic, nontoxic, and stable two-dimensional material, possesses an anisotropic electronic nature. Herein, we study the device performances of the ML SnSe2 metal-oxide-semiconductor FETs (MOSFETs) and deduce their performance limit to an ultrashort gate length (Lg) and ultralow supply voltage (Vdd) by using the ab initio quantum transport simulation. An ultrahigh Ion of 5,660 and 3,145 µA/µm is acquired for the n-type 10-nm-Lg ML SnSe2 MOSFET at Vdd = 0.7 V for high-performance (HP) and low-power (LP) applications, respectively. Specifically, until Lg scales down to 2 and 3 nm, the MOSFETs (at Vdd = 0.65 V) surpass Ion, intrinsic delay time ( τ), and power-delay product (PDP) of the International Roadmap for Device and Systems (IRDS, 2020 version) for HP and LP devices for the year 2028. Moreover, the 5-nm-Lg ML SnSe2 MOSFET (at Vdd = 0.4 V) fulfills the IRDS HP device and the 7-nm-Lg MOSFET (at Vdd = 0.55 V) fulfills the IRDS LP device for the year 2034.

Research Article Issue
High-performance sub-10-nm monolayer black phosphorene tunneling transistors
Nano Research 2018, 11 (5): 2658-2668
Published: 12 May 2018
Downloads:13

Moore's law is approaching its physical limit. Tunneling field-effect transistors (TFETs) based on 2D materials provide a possible scheme to extend Moore's lawdown to the sub-10-nm region owing to the electrostatic integrity and absence of dangling bonds in 2D materials. We report an ab initio quantum transport study on the device performance of monolayer (ML) black phosphorene (BP)TFETs in the sub-10-nm scale (6–10 nm). Under the optimal schemes, the ML BP TFETs show excellent device performance along the armchair transport direction.The on-state current, delay time, and power dissipation of the optimal sub-10-nm ML BP TFETs significantly surpass the latest International Technology Roadmap for Semiconductors (ITRS) requirements for high-performance devices. The subthreshold swings are 56–100 mV/dec, which are much lower than those of their Schottky barrier and metal oxide semiconductor field-effect transistor counterparts.

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