Device performance limit of monolayer SnSe₂ MOSFET

Two-dimensional (2D) semiconductors are attractive channels to shrink the scale of field-effect transistors (FETs), and among which the anisotropic one is more advantageous for a higher on-state current (I_on). Monolayer (ML) SnSe₂, as an abundant, economic, nontoxic, and stable two-dimensional material, possesses an anisotropic electronic nature. Herein, we study the device performances of the ML SnSe₂ metal-oxide-semiconductor FETs (MOSFETs) and deduce their performance limit to an ultrashort gate length (L_g) and ultralow supply voltage (V_dd) by using the ab initio quantum transport simulation. An ultrahigh I_on of 5,660 and 3,145 µA/µm is acquired for the n-type 10-nm-L_g ML SnSe₂ MOSFET at V_dd = 0.7 V for high-performance (HP) and low-power (LP) applications, respectively. Specifically, until L_g scales down to 2 and 3 nm, the MOSFETs (at V_dd = 0.65 V) surpass I_on, intrinsic delay time ( $\tau$), and power-delay product (PDP) of the International Roadmap for Device and Systems (IRDS, 2020 version) for HP and LP devices for the year 2028. Moreover, the 5-nm-L_g ML SnSe₂ MOSFET (at V_dd = 0.4 V) fulfills the IRDS HP device and the 7-nm-L_g MOSFET (at V_dd = 0.55 V) fulfills the IRDS LP device for the year 2034.