Memristors have attracted tremendous interest in the fields of high-density memory and neuromorphic computing. However, despite the tremendous efforts that have been devoted over recent years, high operating voltage, poor stability, and large device variability remain key limitations for its practical application and can be partially attributed to the un-optimized interfaces between electrodes and the channel material. We demonstrate, for the first time, a van der Waals (vdW) memristor by physically sandwiching pre-fabricated metal electrodes on both sides of the two-dimensional channel material. The atomically flat bottom electrode ensures intimate contact between the channel and electrode (hence low operation voltage), and the vdW integration of the top electrode avoids the damage induced by aggressive fabrication processes (e.g. sputtering, lithography) directly applied to the channel material, improving device stability. Together, we demonstrate memristor arrays with a high integration density of 10¹⁰ cm⁻², high stability, and the lowest set/reset voltage of 0.12 V/0.04 V, which is a record low value for all 2D-based memristors, as far as we know. Furthermore, detailed characterizations are conducted to confirm that the improved memristor behavior is the result of optimized metal/channel interfaces. Our study not only demonstrates robust and low voltage memristor, but also provides a general electrode integration approach for other memristors, such as oxide based memristors, that have previously been limited by non-ideal contact integration, high operation voltage and poor device stability.

The two-dimensional transition metal dichalcogenides (TMDs) have attracted intense interest as an atomically thin semiconductor channel for the continued transistor scaling. However, with a dangling bond free surface, it has been a key challenge to reliably integrate high-quality gate dielectrics on TMDs. In particular, the atomic layer deposition of dielectrics on TMDs typically features highly non-uniform nucleation and produces a highly rough or porous dielectric film with rich pinholes that are prone to further damage during the gate integration process. Herein we report a van der Waals (vdW) integration route towards highly reliable gate metal integration on porous dielectrics. The physical lamination process employed by the vdW integration avoids the direct deposition of metal electrodes into porous dielectrics to ensure reliable gate integration and produce low gate leakage devices. The electrical measurements demonstrate the vdW integrated MoS₂ top gate devices exhibit substantially reduced gate leakage current that is about 3–5 orders of magnitude smaller than that with deposited metal electrodes. Furthermore, we show the vdW integration process can be used to create high performance top-gated MoS₂ transistors with ultrathin Al₂O₃ dielectrics down to 1 nm, representing the ultimate dielectric scaling for TMDs transistors. This study demonstrates that vdW integration can enable highly reliable gate integration on relatively low quality dielectrics on TMDs, and opens an interesting pathway to high-performance top-gate transistors using dangling bond free two-dimensional (2D) semiconductors.

Metal-oxide-semiconductor field effect transistors (MOSFET) based on two-dimensional (2D) semiconductors have attracted extensive attention owing to their excellent transport properties, atomically thin geometry, and tunable bandgaps. Besides improving the transistor performance of individual device, lots of efforts have been devoted to achieving 2D logic functions or integrated circuit towards practical application. In this review, we discussed the recent progresses of 2D-based logic circuit. We will first start with the different methods for realization of n-type metal-oxide-semiconductor (NMOS)-only (or p-type metal-oxide-semiconductor (PMOS)-only) logic circuit. Next, various device polarity control and complementary-metal-oxide-semiconductor (CMOS) approaches are summarized, including utilizing different 2D semiconductors with intrinsic complementary doping, charge transfer doping, contact engineering, and electrostatics doping. We will discuss the merits and drawbacks of each approach, and lastly conclude with a short perspective on the challenges and future developments of 2D logic circuit.