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Microwave communication interference cancellation using a programmable integrated photonic processor
Journal of National University of Defense Technology 2026, 48(5): 112-119
Published: 01 October 2026
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Objective

Future wireless transmission systems are expected to operate with higher data rates, wider instantaneous bandwidths, and more compact radio-frequency front ends. Under these conditions, multipath propagation and self-interference in co-located transmitting and receiving platforms become two major factors that degrade receiver performance. Multipath propagation produces delayed replicas of the desired signal and causes inter-symbol interference, while self-interference can occupy the same frequency band as the signal of interest and reduce the available receiver dynamic range. Digital signal processing is flexible, but its sampling-rate, latency, and power-consumption burdens become increasingly heavy when interference suppression is postponed until after analog-to-digital conversion. Discrete microwave photonic systems can perform wideband analog processing, but they are usually built for a single task and require multiple optical paths, fibers, and independent components. The objective of this work is to experimentally verify whether a programmable integrated photonic processor can serve as a reusable analog-domain matrix-weighting core for microwave communication interference suppression, and whether the same chip can be reconfigured to implement both multipath interference cancellation and transmitter-receiver self-interference cancellation.

Methods

A programmable photonic processor based on a two-dimensional Mach-Zehnder interferometer optical switch network was designed and fabricated on a silicon-on-insulator platform. The processor adopts a 16-input and 16-output forward-transmission architecture. It contains tunable Mach-Zehnder interferometer units and optical crossing units, and the thermo-optic phase shifters in the interferometer arms are used to adjust the optical power splitting ratios. After device calibration, these splitting ratios define a configurable transmission matrix, so that different input optical channels can be weighted and routed to selected output ports. For multipath interference cancellation, the processor was configured as a multi-tap microwave photonic filter with positive and negative tap coefficients. Multiple optical wavelengths were weighted by the chip, and the resulting optical signals were modulated with an amplitude-shift keying signal affected by a simulated multipath channel, delayed by a dispersive element, and detected by a photodetector to synthesize the compensation response. A three-path test case was used, including the direct path and two reflected paths with path-length differences of 1.14 m and 2.28 m. Seven optical wavelengths were selected as filter taps, and the tap weights were set according to the calculated compensation response. For self-interference cancellation, the same chip was reconfigured as a positive and negative coefficient weighting network. A linear frequency-modulated reference signal from 1.95 GHz to 2.05 GHz represented the self-interference component, while a composite received signal contained both the interference component and a weaker signal of interest. The photonic processor adjusted the relative amplitudes of the compensation and received paths, and delay matching was used to generate an out-of-phase cancellation component after photodetection.

Results

The multipath interference cancellation experiment demonstrated effective recovery of distorted digital waveforms. For a 2000-bit amplitude-shift keying sequence with an initial bit-error rate of 18.30%, no erroneous bits were observed after the photonic compensation. Two additional distorted sequences with initial bit-error rates of 20.25% and 19.93% were also recovered without observed errors under the same 2000-bit test length. These results show that the chip-configured multi-tap response improved the waveform consistency with the ideal signal and restored the decision margin degraded by multipath-induced inter-symbol interference. In the self-interference cancellation experiment, the interference component originally occupied the 1.95-2.05 GHz working band and masked the signal of interest. After matrix weighting and delay matching, a maximum self-interference suppression of 24.61 dB was obtained within the 100 MHz test band. More importantly, the two experiments were implemented on the same integrated photonic processor through electrical reconfiguration of the transmission matrix, rather than by replacing the chip or rebuilding the entire optical processing path.

Conclusions

The experimental results confirm that a programmable integrated photonic processor can be used as a reconfigurable analog-domain signal-processing core for microwave communication interference suppression. The demonstrated chip does not function merely as a fixed filter or a dedicated canceller; instead, it provides programmable multi-channel weighting that can be mapped to different communication problems. Compared with discrete microwave photonic schemes, the integrated platform has potential advantages in compactness, stability, and functional reuse. Compared with dedicated integrated devices, its processing function can be changed electrically when the channel conditions or task requirements change. Although the present experiments are proof-of-concept demonstrations based on a finite 2000-bit sequence and a 100 MHz self-interference test band, they provide direct evidence that multipath decoupling and self-interference suppression can both be partly moved into the analog photonic front end. This capability is promising for reducing receiver dynamic-range pressure, sampling-bandwidth requirements, and the complexity of back-end digital equalization or cancellation in future full-duplex, radar-communication integrated, and adaptive wireless systems. Future work should further reduce chip insertion loss and tuning power, improve thermo-optic tuning speed, develop automatic matrix calibration, and evaluate the processor under longer bit sequences, dynamic channels, and more complex modulation formats.

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