Due to the influence of the junction temperature distribution in multichip modules, the fatigue degree of the chip solder layer varies in the service process, which leads to the intensification of the junction temperature distribution. And further affects the accurate assessment of the reliability of the multichip module under long-term use. This paper establishes a junction temperature assessment model that takes into account the spatial distribution of chip solder layer fatigue in multichip modules. This model characterizes the mutually exacerbating effects between the spatial distributability of solder layer fatigue and the degree of junction temperature inhomogeneity in multichip modules. Further, the accuracy of life prediction and junction temperature assessment over the full life cycle of multichip modules is realized.

According to the feedback relationship between the junction temperature and the spatial distribution of chip solder layer fatigue, a junction temperature assessment model considering the chip solder layer fatigue and its spatial distribution is established. A thermal network model based on power flow is established. Further, the time-varying cumulative damage of the spatial distribution of chip solder layer fatigue is taken into account. As a result, the mutually exacerbating effect between the spatial distribution of chip solder layer fatigue and the degree of junction temperature inhomogeneity is characterized. By continuously updating the thermal impedance parameters of the solder layer in the thermal network model during the fatigue process of the device, the junction temperature distribution over the whole life cycle of the multichip module can be accurately predicted.

Taking a multichip parallel IGBT module with the power rating of 1700V/600A as an example, the accuracy of the developed model is validated. The degree of spatial distribution of fatigue in the solder layer reaches 36.2% and 42.7% when the power cycling currents are 300A and 400A. The degree of spatial distribution of fatigue in the solder layer increases with the increase of junction temperature. In addition, after considering the influence of the spatial distribution of solder layer fatigue on the junction temperature prediction model, the errors of junction temperature maximum and junction temperature fluctuation are reduced from 4.9℃ and 7.4℃ to less than 1℃.

In this paper, the exacerbation between junction temperature imbalance and the spatial distribution of chip solder layer fatigue in multichip IGBT power modules is investigated. Firstly, a thermal network model based on power flow is established. The model jointly considers the time-varying cumulative damage of the spatial distribution of chip solder layer fatigue. Thus, a junction temperature assessment model that takes into account the spatial distribution of chip solder layer fatigue is established. The thermal impedance parameters of the solder layer in the thermal network model are continuously updated during the fatigue process of the device. The distribution of junction temperature over the whole life cycle of a multichip module can be accurately predicted. In addition, the error between the junction temperature predicted by considering the fatigue spatial distribution and that predicted without considering the fatigue spatial distribution is compared with experimental results. The results show that if the spatial distribution of solder layer fatigue is not taken into account, the error in junction temperature prediction increases with the cumulative damage, and further affects the reliability assessment of the module. It is also revealed that the degree of spatial distribution of solder layer fatigue increases linearly with the degree of device damage. And the greater the damage, the more serious the degree of spatial distribution of fatigue.