Carbon nanotube-based (CNT-based) transistors are promising devices for next-generation electronic devices owing to their extraordinary electrostatics, high carrier mobility, and compatibility with low-temperature processing. However, in the widely used bottom-gate configuration, gate topography as a nanoscale physical parameter and its role in governing interfacial states and charge dynamics in carbon nanotube transistors remains insufficiently studied, despite its significant influence on interface charge trapping, hysteresis, bias-stress stability, and overall device performances. This work systematically investigates the role of gate topography by introducing an atomically smooth amorphous metal (ZrCuAlNi) as bottom-gate electrode, and comparing it with conventional polycrystalline metal gate. Owing to its homogeneous, grain-boundary-free microstructure, the amorphous metal gate enables the formation of a high-quality gate dielectric interface, which reduces the interface trap density by 39.27% in average and consequently lowers the device hysteresis voltage by about 50%, accompanied by improved carrier mobility, on-state current and bias stress stabilities, while maintaining the on/off ratio (>10⁶). These results reveal that nanoscale gate surface morphology plays a critical role in regulating interfacial trap dynamics and charge transport in CNT transistors. The interface de-pinning mechanism demonstrated here with ultrasmooth gates is expected to be broadly applicable to other semiconductors. Consequently, this work provides both a specific material solution for stable CNT transistors and new insights into interface engineering strategies for carbon nanotube electronics and other carbon-based electronic devices.