A networks-on-chip (NoC) cost-effective design method was given based on the globally-asynchronous locally-synchronous (GALS) interconnect structure. In this method, the synchronous mode was used to transmit data among routers, network interface (NI), and intellectual property (IP) via a synchronous circuit. Compared with traditional methods of implementing GALS, this method greatly reduces the transmission latency and is compatible with existing very large scale integration (VLSI) design tools. The platform designed based on the method can support two kinds of packetizing mechanisms, any topology, several kinds of traffic, and many configurable parameters such as the number of virtual channels, thus the platform is universal. An NoC evaluation methodology is given with a case study showing that the platform and evaluation methodology work well.

The Ethernet over E1 approach, which takes advantage of widely deployed telecom networks, is an efficient and economical way to interconnect two Ethernets in different regions. Two Ethernet over E1 schemes, namely a byte granularity scheme and a frame granularity scheme are discussed. The byte granularity scheme partitions Ethernet frames into several pieces for transmission and has a strict requirement on the maximum delay difference of multiple E1 links. To solve this problem, the newly proposed frame granularity scheme transmits separately each frame through E1 links without any partitioning. The architecture designs of both schemes are presented. This paper evaluates the throughput and delay performances of both schemes, both analytically from results calculated from delay models and using test results from field programmable gate array (FPGA) implementation. Although the frame granularity scheme has a slightly worse delay performance, it has a higher throughput, and is the only choice able to overcome large delay differences of the E1 links.