This paper presents a new combined AC/DC-coupled output averaging technique for input amplifier design of flash analog-to-digital converters (ADC). The new offset averaging design technique takes full advantage of traditional DC-coupled resistance averaging and AC-coupled capacitance averaging techniques to minimize offset-induced ADC nonlinearities. Circuit analysis allows selection of optimum resistance and capacitance averaging factors to achieve maximum offset reduction in ADC designs. The new averaging method is verified in designing a 4 bit 1 Gs/s flash ADC that is implemented in foundry 0.13 μm CMOS technology.

Electrostatic discharge (ESD) induced parasitic effects have serious impacts on performance of radio frequency (RF) integrated circuits (IC). This paper discusses a comprehensive noise analysis procedure for ESD protection structures and their negative influences on RF ICs. Noise figures (NFs) of commonly used ESD protection structures and their impacts on a single-chip 5.5 GHz low-noise amplifier (LNA) circuit were depicted. A design example in 0.18 μm SiGe BiCMOS was presented. Measurement results confirm that significant noise degradation occurs in the LNA circuit due to ESD-induced noise effects. A practical design procedure for ESD-protected RF ICs is provided for real-world RF IC optimization.

As integrated circuits (IC) technologies advance into very-deep-sub-micron (VDSM), electrostatic discharge (ESD) failure becomes one of the most devastating IC reliability problems and on-chip ESD protection design emerges as a major challenge to radio frequency (RF), analog, and mixed-signal (AMS) IC designs. This paper reviews key design aspects and recent advances in whole-chip ESD protection designs for RF/AMS IC applications in CMOS technologies.