Decreasing the power supply voltage in dynamic voltage frequency scaling to save power consumption may introduce extra delays in CMOS circuits, which may cause errors. This paper presents the probabilistic delay fault model (PDFM), which describes the probability of an error occurring as a function of the power supply voltage and the clock period in synchronous CMOS circuits. In a wide range of applications (graphic, video, digital filtering, etc.), errors occurring with low probability and not remaining for a long time are acceptable. For combinational circuits which have long critical paths with low probability of excitation, a performance increase is achieved with a certain rate of errors determined by the PDFM compared with the traditional design which considers the worst case. The PDFM applied to array multipliers and ripple carry adders shows the agreement of the predicted probabilities with simulated delay histograms to support the practicality of using the PDFM to select power supply voltage and clock period in dynamic voltage frequency scaling circuits with tolerable error rates.

Implementing video applications on emerging multi-core processors is a promising technique for personal, real-time multi-media applications. However, when porting the legacy parallel video encoders developed for clusters to shared-memory multi-cores, the existing parallel algorithms result in workload imbalances on different cores and communication inefficiencies. This paper describes a strip-wise parallel scheme to balance workloads and a hybrid communication mechanism to reduce communication overhead. The implementation of the H.264 parallel encoder on an eight CPU Intel Xeon system achieves 5x to 6x speed-up over a single thread encoder and achieves a 29% performance improvement over the commonly used master-slave schemes on clusters. The paper also gives further analysis on scalability, parallel efficiency, workload balance, and communication overhead as the number of cores varies.

This paper illustrates the importance of the configuration of function units and the change of an application’s critical path when using instruction set extension (ISE) with multi-issue architectures. This paper also presents an automatic identification approach for customized instruction without input/output number constraints for multi-issue architectures. The approach identifies customized instructions using multiple attribute decision-making based on the analysis of several attributes for each candidate node. Tests indicate that the approach achieves higher speedup ratios than previous approaches，as well as less area cost. In addition，this approach provides designers with multiple candidate designs.

This paper presents an instruction scheduling and cluster assignment approach for clustered very long instruction words (VLIW) processors. The technique produces high performance code by simultaneously balancing instructions among clusters and minimizing the amount of inter-cluster data communications. The scheme is evaluated based on benchmarks extracted from UTDSP. Results show a significant speedup compared with previously used techniques with speed-ups of up to 44%, with average speed-ups ranging from 14% (2-cluster) to 18% (4-cluster).

The cost of the central register file and the size of the program code limit the scalability of very long instruction word (VLIW) processors with increasing numbers of functional units. This paper presents the architectural design of a six-way VLIW digital signal processor (DSP) with clustered register files. The architecture uses a variable length instruction set and supports dynamic instruction dispatching. The one-level memory system architecture of the processor includes 16-KB instruction and data caches and 16-KB instruction and data on-chip RAM. A compiler based on the Open64 was developed for the system. Evaluations show that the processor is suitable for high performance applications with a high code density and small program code size.

A low power digital operational transconductance amplifier (OTA) was developed for low voltage switched capacitor applications. The OTA has a high slew rate (SR) and a large open loop gain with a differential pseudo-two-stage Class-AB structure. A fully compensated depletion mode capacitor is used in the switched capacitor common mode feedback block instead of a metal-insulator-metal (MIM) capacitor to reduce the fabrication cost. Simulations show that with a 1.0-V supply voltage and a 34-pF load at each output terminal, this digital differential pseudo-two-stage Class-AB OTA realized in 0.13-μm technology achieves a 63.5-dB DC gain and a 0.83-V output swing. The slew rate is ±16.29 V/μs and the total power dissipation is only 82 μW.

The rapid development of multimedia techniques has increased the demands on multimedia processors. This paper presents a new design method to quickly design high performance processors for new multimedia applications. In this approach, a configurable processor based on the very long instruction-set word architecture is used as the basic core for designers to easily configure new processor cores for multimedia algorithm. Specific instructions designed for multimedia applications efficiently improve the performance of the target processor. Functions not implemented in the digital signal processor (DSP) core can be easily integrated into the target processor as user-defined hardware to increase the performance. Several examples are given based on the architecture. The results show that the processor performance is enhanced approximately 4 times on the H.263 codec and that the processor outperforms both DSPs and single instruction multiple data (SIMD) multimedia extension architectures by up to 8 times when computing the 2-D-IDCT.

Network-on-chip (NoC) technology enables a new system-on-chip paradigm, the system-on-network-on-chip (SoNoC) paradigm. One of the challenges in designing application-specific networks is modeling the on-chip system behavior and determining on-chip traffic characteristics. A universal object message level model for SoNoC was defined and an object-oriented methodology was developed to implement this model in hardware and software. The model supports “object to core” synthesis and “function invoking to network” mapping. A case study of an H.263 system verifies the model and methodology. System prototypes are easily built and on-chip traffic can be observed using the SoNoC model to provide real benchmarks for on-chip network design.