Quasi-one-dimensional (quasi-1D) van der Waals (vdW) materials represent an emerging frontier in nanoscience, yet the synthesis of their metastable phases remains a significant challenge, as exemplified by W₆Te₆, whose formation is precluded by the thermodynamically favored growth of the stable WTe₂ phase. Here, we report a robust, kinetically-controlled anion-exchange (KCAE) strategy, involving a two-step process: A sputtered tungsten (W) film is converted into a stable, vertically-grained 2H-WS₂ template, followed by controlled tellurization. The high activation energy required to break the W–S bonds acts as a kinetic barrier that inhibits the formation of the WTe₂ phase, enabling the precise isolation of the metastable W₆Te₆ phase. Mechanistic studies indicate that the conversion initiates via heterogeneous nucleation at the exposed edges of the vertical WS₂ grains. This KCAE framework enables the first-ever synthesis of uniform, 1-inch wafer-scale W₆Te₆ films. Furthermore, this template-based method is fully compatible with standard photolithography, allowing for the pre-patterning of complex W₆Te₆ nanostructures. Our work establishes a generalizable platform for the wafer-scale synthesis of metastable vdW materials previously inaccessible by conventional methods.

The integration of high-performance two-dimensional (2D) semiconductor devices is fundamentally bottlenecked by severe Fermi-level pinning (FLP) at the metal-semiconductor interface. Direct deposition of high-work-function, high-melting-point metals typically inflicts structural damage on the 2D lattice, generating interfacial defects that strongly pin the Fermi level. Here, we report a damage-free metallization strategy utilizing low-temperature phase engineering to achieve highly conductive, weakly pinned contacts. We employ a low-energy evaporation of tellurium (Te) as a non-destructive buffer layer, which effectively shields the underlying 2D channel during the subsequent deposition of palladium (Pd). Through a precisely controlled low-temperature annealing process, the Te and Pd layers undergo a solid-state reaction, transforming into a highly conductive, high-work-function metallic PdTe₂ phase. We demonstrate that PdTe₂-contacted MoTe₂ field-effect transistors (FETs) exhibit significantly enhanced electrical performance compared to those with directly deposited Pd or unannealed Te/Pd contacts. Furthermore, applying this strategy to WSe₂ FETs shifts the transport from a strongly pinned n-type behavior—characteristic of direct Pd contacts—to a weakly pinned ambipolar characteristic with superior electrical properties. Crucially, the low thermal budget of this phase-transformation process offers a scalable pathway for integrating pristine, high-performance 2D electronics.