A multi-level area optimization algorithm for logic circuits based on error rate allocation is proposed, taking into account that the approximate optimization effects of a logic function under the same error rate constraint differ when the function is expressed in two-level or multi-level forms and that there is an equivalent conversion between two-level and multi-level forms. This algorithm consists of a two-level error rate estimation technique, an error rate coefficient search method for error rate division, and a two-level/multi-level approximate optimization method. The proposed algorithm is implemented using C, the commands of a system for sequential logic synthesis and formal verification (ABC) tools and tested with Microelectronics Center of North Carolina (MCNC) benchmarks. The experimental results show that, compared to the ABC tools, with the 5% error rate, the proposed algorithm achieves 42.36% and 25.15% in area and delay optimization, respectively. Compared to those approximate methods that only use the multi-level approximation method, further improvement in area and delay can be obtained by 5.05% and 9.36%, respectively.

Given that the current area optimization at the hardware description language (HDL) level using approximate computing techniques is unable to effectively utilize the optimization space provided by quality-of-result (QoR) constraints, an approximate optimization algorithm for arithmetic circuits is proposed. This algorithm includes the selection mechanism of the proposed approximate operations, internal signal bit-width reduction, arithmetic operator replacement, and approximate arithmetic cell circuits calling. The proposed algorithm is programmed in C and the circuit area is estimated by Design Compiler. The experimental results show that under the constraint of QoR, compared with the non-approximate optimization result, the average area saving is 55.2%. The suggested approach can further increase the average area save by 24.9% when compared to the reported approximate strategy.