With the rapid rise of domestic accelerators and the growing demand for efficient cryptographic algorithm implementations, optimizing the performance of domestic commercial cryptography on homegrown hardware platforms has become a critical research challenge. This paper focuses on utilizing the Chinese Hygon Deep-learning Computing Unit (DCU) as an acceleration platform and proposes a high-performance SM4 encryption implementation. First, we design a collaborative CPU/DCU computing framework, where the CPU handles task scheduling while the DCU performs parallel execution of computationally intensive tasks. Additionally, we leverage the data copy engine of the DCU and employ HIP (heterogeneous-computing interface for portability) stream-based data transmission to enhance computational efficiency. Second, we propose an optimized hierarchical memory access strategy by merging multiple sets of computational data for unified transfer and employing a hierarchical storage scheme based on data characteristics to improve memory access efficiency. Furthermore, we employ GCN (Graphics Core Next) ISA (Instruction Set Architecture) inline assembly to achieve constant-time computation, which enhances both security and computational performance. Finally, we support both single-key and multi-key encryption modes, optimizing memory access and parallel computation for each. The experimental results show that our optimized SM4 implementation HI-SM4 achieves a throughput of 161.81 Gbps in the multi-key encryption mode and up to 730.88 Gbps in the single-key encryption mode. Compared with the best existing SM4 implementations on CPU, FPGA, and GPU platforms, our approach achieves performance improvements of 28.22x, 4.50x, and 1.36x, respectively. Our research presents a feasible framework for efficiently implementing indigenous cryptographic algorithms on domestically developed hardware accelerators, thereby contributing to the advancement of high-performance cryptographic computation.

Hash functions are essential in cryptographic primitives such as digital signatures, key exchanges, and blockchain technology. SM3, built upon the Merkle-Damgard structure, is a crucial element in Chinese commercial cryptographic schemes. Optimizing hash function performance is crucial given the growth of Internet of Things (IoT) devices and the rapid evolution of blockchain technology. In this paper, we introduce a high-performance implementation framework for accelerating the SM3 cryptography hash function, short for HI-SM3, using heterogeneous GPU (graphics processing unit) parallel computing devices. HI-SM3 enhances the implementation of hash functions across four dimensions: parallelism, register utilization, memory access, and instruction efficiency, resulting in significant performance gains across various GPU platforms. Leveraging the NVIDIA RTX 4090 GPU, HI-SM3 achieves a remarkable peak performance of 454.74 GB/s, surpassing OpenSSL on a high-end server CPU (E5-2699V3) with 16 cores by over 150 times. On the Hygon DCU accelerator, a Chinese domestic graphics card, it achieves 113.77 GB/s. Furthermore, compared with the fastest known GPU-based SM3 implementation, HI-SM3 on the same GPU platform exhibits a 3.12x performance improvement. Even on embedded GPUs consuming less than 40W, HI-SM3 attains a throughput of 5.90 GB/s, which is twice as high as that of a server-level CPU. In summary, HI-SM3 provides a significant performance advantage, positioning it as a compelling solution for accelerating hash operations.