Spin-orbit torque magnetic random access memory (SOT-MRAM), which is theoretically predicted with “unlimited” endurance, has been regarded as a promising alternative to conventional static random access memory (SRAM)-based L1 to L3 caches in advanced complementary metal-oxide-semiconductor (CMOS) technology nodes. However, contrary to the predicted “unlimited” endurance, the experimental test reveals that practical SOT-MRAM fails upon reaching an endurance limit, and the underlying mechanism remains unclear. We also lack information on how these limits depend on the materials or structures used, particularly at the array level. In this work, we conducted a thorough investigation of the endurance performance of SOT-MRAM arrays through cycling tests under various voltages and thermal stress conditions. Experimental results show that SOT-MRAM failures mainly happen due to thermal interdiffusion in the magnetic tunnel junctions (MTJs). This process is largely caused by Joule heating over 180 K in the SOT channel during write operations. This heat generation creates a fundamental limitation on achieving “unlimited” endurance in practical implementations. To enhance the endurance of SOT-MRAM, we proposed several optimization strategies from the perspectives of material and structure engineering, including optimizing the SOT channel material and reducing the SOT channel length. Through these optimization measures, we successfully improved the endurance of SOT-MRAM to over 10¹⁸ cycles at 125 °C, meeting the requirements for “unlimited” operation (≥ 10¹⁷ cycles) in edge computing applications. This provides design guidelines for realizing SOT-MRAM’s potential as a candidate to SRAM in high-performance cache hierarchies.