Carbon nanotubes (CNTs) offer exceptional electronic properties, making them promising candidates for high-performance thin-film transistor (TFT) applications. However, conventional fabrication exposes CNT surfaces to resists, leaving persistent residues that degrade dielectric and contact interfaces, resulting in reduced on-state current, lower mobility, poor subthreshold swing, and device nonuniformity. Existing approaches, including ultraviolet-ozone treatment, wet etching, or sacrificial layers, partially mitigate contamination but cannot fully eliminate residues and often limit device scaling. Here, we introduce a fabrication process for top-gate CNT TFTs that achieves resist-contamination-free interfaces using atomic layer etching (ALE) technology. A Y₂O₃ sacrificial layer defines the active region, enabling high-quality atomic layer deposition of the gate dielectric. Selective ALE precisely etches the dielectric above source/drain regions, with Ar plasma power tuned to minimize damage to underlying CNTs, yielding excellent metal contacts. CNT TFTs fabricated with this approach demonstrate a maximum on-state current of 27.1 μA/μm and peak mobility of 141 cm²/(V·s) at a channel length of 2 μm, and also exhibit excellent performance uniformity, low contact resistance, and low interface trap density. These devices surpass other CNT, low-temperature polycrystalline silicon (LTPS), indium-gallium-zinc-oxide (IGZO), and transition metal dichalcogenide (TMDC) TFTs in performance, scalability, and process simplicity. This work provides a scalable pathway towards high-performance CNT TFTs and also suggests potential for miniaturized transistors, as ALE’s vertical, highly directional etch preserves lateral dimensions.