Analog-to-Digital Converter (ADC) is the bridge connecting the analog world and the digital world. With the development of circuit techniques and manufacturing process, its performance indicators have made great progress. The classification and performance characteristics of ADCs are firstly introduced, and then a description is made on the basic principles and technological development of ADCs of different structures including directions: high-speed and high-resolution ADCs. For high-speed ADCs, this article focuses on performance optimization techniques for SAR ADCs and Pipelined-SAR ADCs, such as CDAC controlling methods and comparator design, non-binary redundancy, loop-unrolled, and inter-stage redundancy. For high-resolution ADCs, the various types of Delta-Sigma ADCs and their advantages are analyzed, and the technical characteristics of Zoom ADCs and NS-SAR ADCs introduced. Some new types of hybrid-architecture ADCs are also summarized, describing their composition and research progress.

In pipelined-successive approximation register analog-to-digital converter (pipelined-SAR ADC), it is necessary to use large-open-loop gain operational amplifiers to improve the gain accuracy of closed-loop residual amplifications. The proposed ring amplifier uses a gain-enhanced output stage to improve the open-loop gain and stability, achieving an open-loop gain of over 90 dB and significantly reducing the residue gain errors without any calibration techniques, meeting the accuracy requirement of a 16 bit ADC. The ADC is implemented in the 65 nm CMOS process with an active area of 0.256 mm². At a sampling rate of 25 MS/s and with Nyquist-rate input, the proposed ADC achieves simulated signal-to-noise distortion ratio (SNDR) and spurious free dynamic range (SFDR) of 77.8 dB and 96.8 dB, respectively, with a power consumption of 2.8 mW. The proposed ADC achieves Walden and Schreier figure-of-merit (FoM) of 18.0 fJ/conversion-step and 174.3 dB, respectively.