Due to the low complexity and flexible construction, polar code has become one of the most popular channel codings in wireless communication. However, the conventional successive cancellation (SC) decoder suffers from the modest performance. To deal with this issue, some improved decoders, such as successive cancellation stack (SCS) and successive cancellation list (SCL) , are developed with significant improvement of bit error ratio. However, the performance improvement of these methods is at the cost of high complexity, especially in the procedure of path selection. In this work, we propose a new hardware architecture of path selection by combining the monotone sorting of groups with the parallel comparison, which enhances the performances of hardware efficiency and resource utilization. By exploiting our proposed architecture, the results of the implementation on field programmable gate array (FPGA) verify that the hardware consumptions of the look up table (LUT), register and block random access memory (BRAM) are reduced by 24.06% , 56.42% and 39.29% respectively. And the throughput is improved by 24.38% as compared with the existing architectures.