Parked vehicle assisted edge computing (PVEC) is effective to alleviate the imbalance between supply and demand of resources in vehicular edge computing, by utilizing the idle resources in parked vehicles (PVs). However, the computing services provided by the PVs can be abruptly aborted due to uncertain parking behaviours. This makes it hard to meet the requirements of users on service reliability. To address this issue, this paper formulates an optimization problem for service reliability guarantee. Then, a task replication technique is introduced to transform the formulated problem into a replication offloading problem, with the goal of minimizing the average completion time of task replications. The NP-hardness of the formulated problem is proved. A greedy algorithm (GA) is proposed to solve the formulated problem, by carefully offloading the replicas of the tasks with large data sizes to the PVs, which can provide the computing services with service guarantee and short completion time. Meanwhile, an enhanced genetic algorithm (EGA) is proposed to refine the solution generated by the proposed algorithm GA. Experimental results show that the proposed GA and EGA algorithms outperform the baseline algorithms in terms of the average completion time of task replications for different requirements of users on service reliability.

Memristors, originally exploited for nonvolatile storage, are now intensively investigated as logic primitives capable of in-memory computing, offering a promising solution to break the “memory wall”. However, when targeting the design of large and complex circuits, existing synthesis flows restricted to a single memristive logic lack the flexibility, leading to results that the performance metrics of circuits fall short of design targets. In this work, a dual-domain synthesis framework is proposed that synergistically combines memristor-based implication (IMP) logic and not-implication (N-IMP) primitives. By systematically analyzing their mapping and scheduling characteristics on circuit netlists, three cooperative strategies are introduced during the process of technology-independent optimization: optimization for rewriting the minimal-substructure, disjunctive/conjunctive duality selection for multiplexers, and collective refactoring of multi-fan-out clusters. The proposed methods achieve high-performance graph topology transformation and scheduling. Experimental results show that, compared with ABC tool, the proposed methods achieve the reduction of number of nodes after mapping by 17.32%. Furthermore, the proposed methods achieve the improvement in area overhead by 61.5% during the process of scheduling, when compared with the state-of-the-art work (AND-OR) .

With the continuous development of convolutional neural networks (CNNs) in deep learning, computational complexity and hardware resource consumption have become the significant bottlenecks limiting computational efficiency. This paper proposes a hybrid processing unit (HPE) based on Block Floating Point (BFP) , which optimizes the design of the convolution computation unit in the hardware architecture by replacing the traditional Look-up Table (LUT) with DSP and employing data packing techniques. This design enables flexible switching between INT4 and BFP8 computation modes, significantly improving computational performance and reducing hardware resource consumption. Experimental results show that, when using a hybrid precision (INT4 and BFP8) computation mode, HPE significantly reduces LUT and FF overhead, with hardware resource utilization efficiency increasing by 123.40% and 58.16%, respectively, compared to the baseline. Furthermore, the data packing techniques enable the HPE to achieve 2× higher throughput than the conventional implementations. This study provides an efficient hardware solution for deep learning acceleration, with broad potential applications, especially in deep learning tasks requiring high computational efficiency and resource optimization.