With the continuous increase in the number of stacking layers in 3D NAND flash memory, the aspect ratio caused by deep hole etching processes also increases accordingly. The resulting taper angle leads to a broadening of the threshold voltage distribution of memory cells, adversely affecting device storage reliability. Current solutions to this problem primarily include process-based methods such as etching optimization and channel compensation, or strategies like error correction coding and read-retry. However, these approaches generally face challenges such as implementation complexity and high hardware overhead. To overcome these limitations and effectively mitigate the impact of the taper angle, a simulation model of a memory string incorporating taper angles is first constructed based on the Sentaurus TCAD platform, validating and analyzing the influence of deep hole taper on the threshold voltage distribution gradient. On this basis, a strategy for dynamic optimization of the pass voltage amplitude in adjacent cells is proposed. This strategy differentially optimizes the pass voltage of word lines adjacent to the target memory cell according to its vertical position in the memory string, thereby accurately compensating for the longitudinal voltage gradient induced by channel taper. Simulation results demonstrate that compared to conventional programming strategy, the proposed strategy optimizes the maximum voltage difference and the standard deviation of distribution, achieving reductions of 62.4% and 61.4%, respectively, in linear mode, and 63.7% and 64.3% in nonlinear mode, while constraining the threshold voltage disturbance of adjacent cells within 3 mV and maintaining stable programming speed.

Solid State Disks based on 3D triple cell NAND flash has becoming a dominant storage medium in mass storage systems due to their high storage density and low cost per bit. With the rapid development of technologies, 3D NAND flash chips are becoming less reliable with high storage densities. Reduced reliability and overly conservative manufacturers' formulation of lifetime nominal values result in flash chips being prematurely phased out before reaching their actual lifespan with unnecessary waste. Lifetime prediction of flash chips through machine learning-based prediction models can optimize storage strategies to effectively extend lifetime and reduce losses. However, due to the differences in production processes, the error characteristics of flash memory chips are somewhat different from each other, which affects the accuracy of the life prediction of flash memory chips. In this paper, we experimentally find that the bit error rate of data retention errors can be used to characterize the number of program/erase cycles times, and propose to stimulate the interference between word-lines by writing specific contents to adjacent word-lines, which can effectively reduce the elapsed time and improve the accuracy of the life time prediction. Experimental results show that the elapsed time can be shorten by about 90.9%, and the prediction accuracy can be improved by 33.3 percentage points.

3D NAND Flash memory has emerged as a mainstream data storage medium due to its high performance, high storage density and low power consumption. However, its reliability is significantly affected by multiple factors such as limited program/erase endurance, data retention issues, read disturb, and inter-layer variations, which introduce noise and degrade performance. To address these challenges, this paper performs noise injection experiments on 3D NAND Flash memory to systematically investigate the bit error rate (BER) under various noise coupling conditions. By analyzing the experimentalresults, the corresponding threshold voltage distributions were extracted, and a reference voltage model tailored to different noise conditions was developed to improve the reliability of the Flash memory. Experimental results demonstrate that the proposed reference voltage model effectively reduces the BER of 3D NAND Flash memory under noise interference by up to 46% when compared to the default reference voltage. The reference voltage model provides an effective technical solution to improve the storage reliability of 3D NAND Flash memory in noisy environments, and it is expected to promote its wide application in high-reliability storage domains.