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3D integration of van der Waals high-κ dielectrics and semiconductors for low-power CFETs
Nano Research 2026, 19(7): 94908307
Published: 01 June 2026
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Atomically thin two-dimensional (2D) van der Waals (vdW) layered semiconductors with dangling-bond-free surfaces and excellent electronic properties are considered as alternative channel materials to address the challenges faced by the miniature transistors at next-generation technology nodes. However, the scarcity of high-dielectric-constant (κ) vdW single-crystalline gate dielectrics that are well compatible with them poses an obstacle to the practical applications of 2D semiconductors. Here, we report the synthesis of high-κ vdW Bi2TeO5 single crystals via chemical vapor deposition, as well as their applications as gate dielectrics. The as-grown vdW Bi2TeO5 shows in-plane ferroelectricity, featuring a high Curie temperature and a remarkable dielectric constant (κ ≈ 48), which is currently the highest value reported for various vdW dielectrics. The 2D semiconductor-based transistors gated by Bi2TeO5 crystal achieve an on-off current ratio exceeding 107, a near-Boltzmann-limit subthreshold swing, and a low gate leakage current. Furthermore, the three-dimensional-stacked complementary field-effect transistor inverters are constructed by integrating 2D vdW semiconductors and dielectrics, and exhibit a voltage gain of 4 and a power consumption of 193 pW at a low supply voltage of 0.3 V. Our work demonstrates that 2D vdW Bi2TeO5 is a promising high-κ single-crystalline gate dielectric and opens up a new opportunity for highly scalable, low-power 2D electronics.

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