Real-time digital audio processing plays a crucial role in modern electronic systems, such as mobile devices, communication platforms, and multimedia applications. However, ensuring high-performance, low-latency processing under hardware constraints remains a significant challenge, particularly when integrating audio codec chips with FPGA platforms. This paper presents the design and implementation of a real-time digital audio processing system using field-programmable gate array (FPGA) technology and the WM8731 audio codec. Firstly, a robust Inter-Integrated Circuit (I²C) interface is developed to configure the WM8731 codec, ensuring accurate initialization and stable operation. Secondly, a serial-to-parallel adaptor (s2p_adaptor) is designed to convert inter-IC sound (I²S) serial audio data into parallel format for digital processing, synchronized with bit and frame clocks. Finally, an 8-tap finite impulse response (FIR) filter is implemented using very high speed integrated circuit (VHSIC) hardware description language (VHDL) to enhance audio quality by suppressing high-frequency noise. All modules are synthesized in Quartus II and verified through ModelSim simulations and practical testing on an Altera DE1 development board. Timing diagrams based on the WM8731 datasheet and internal clock signals ensure precise synchronization. Experimental results demonstrate the effectiveness of the system, while final analysis highlights areas for further optimization and future improvements. Beyond audio applications, the proposed architecture is also adaptable to other real-time signal processing tasks, such as biomedical monitoring, radar front-end filtering, and image preprocessing. This extensibility enhances the system’s relevance in broader embedded and communication contexts.

With the expansion and increasing complexity of data center networks (DCNs), network fault-tolerance has become increasingly important. RRect is a server-centered DCN with a good interconnection structure. In this paper, we propose a fault-tolerant routing algorithm RRFP under a conditional fault pattern of RRect, which can find a fault-free path between any two fault-free vertices. Firstly, we study a fault pattern of RRect in the case of restricted faulty vertex sets, $\{1,2\}$-restricted connectivity. It is about $\{2,3\}$ times RRect’s traditional connectivity, indicating that $\{1,2\}$-restricted connectivity better evaluates the fault-tolerant capability. Secondly, we design an effective fault-tolerant routing algorithm RRFP under the conditional fault pattern of RRect, and RRFP can accommodate more faulty vertices. Finally, we conduct experiments on RRFP to evaluate its performance. The experimental results show that in terms of the running time, as parameters $n$ and $k$ change, RRFP outperforms Dijkstra’s algorithm by 64%–84% and Breadth-First-Search (BFS) by 56%–71%. The running time of all the three algorithms is very short as parameter $m$ changes. In terms of the constructing path length, as parameters change, RRFP outperforms BFS by 12%–19%. Moreover, the path constructed by RRFP approaches the shortest path of Dijkstra’s algorithm. Moreover, RRFP still maintains a low transmission failure rate (TFR) and high reliability even with an increase in the number of fault elements.