Steric hindrance of long-chain ligands leads to abundant unpassivated dangling bonds on quantum dots (QDs), which significantly impair the efficiency and operational stability of QD light-emitting diodes (QLEDs), especially in ultra-small pixel devices. Here, we utilize a small molecule with strong coordination capability, zirconium acetylacetonate (Zr(acac)₄), to precisely repatch the residual surface defects of QDs. The acetylacetonate anions with high agility and flexibility can overcome the obstacles of spatial hindrance imposed by long-chain ligands, readily diffuse to the surface of QDs and strongly anchor onto the unsaturated zinc. This reconstruction enhances quantum yield of QDs and suppresses exciton quenching typically at the QD/ZnO interface. Additionally, the injection of excessive carriers is suppressed, preventing electron leakage to the hole transport layer (HTL). Consequently, the optimized pixel-less QLEDs achieve an ultrahigh external quantum efficiency (EQE) of 34.3% and an operational T₉₅@1000 cd/m² lifetime of 19,450 h, which are markedly superior to the unmodified counterparts (EQE = 27.5%, T₉₅@1000 cd/m² = 4974 h). The resultant high-resolution QLEDs exhibit a champion-level EQE of 25.3% at approximately 10,000 pixels per inch (PPI).

Graph convolution networks (GCN) have demonstrated success in learning graph structures; however, they are limited in inductive tasks. Graph attention networks (GAT) were proposed to address the limitations of GCN and have shown high performance in graph-based tasks. Despite this success, GAT faces challenges in hardware acceleration, including: 1) The GAT algorithm has difficulty adapting to hardware; 2) challenges in efficiently implementing Sparse matrix multiplication (SPMM); and 3) complex addressing and pipeline stall issues due to irregular memory accesses. To this end, this paper proposed SH-GAT, an FPGA-based GAT accelerator that achieves more efficient GAT inference. The proposed approach employed several optimizations to enhance GAT performance. First, this work optimized the GAT algorithm using split weights and softmax approximation to make it more hardware-friendly. Second, a load-balanced SPMM kernel was designed to fully leverage potential parallelism and improve data throughput. Lastly, data preprocessing was performed by pre-fetching the source node and its neighbor nodes, effectively addressing pipeline stall and complexly addressing issues arising from irregular memory access. SH-GAT was evaluated on the Xilinx FPGA Alveo U280 accelerator card with three popular datasets. Compared to existing CPU, GPU, and state-of-the-art (SOTA) FPGA-based accelerators, SH-GAT can achieve speedup by up to 3283 $\times$, 13 $\times$, and 2.3 $\times$.