The cold sintering process (CSP) is recognized as an emerging low-temperature densification strategy that provides a scalable and energy-efficient route for producing advanced ceramics and composite materials. However, its application has thus far been largely confined to small samples (diameter <15 mm), leaving the behavior of large-sized electronic ceramics scarcely explored. Here, a multidoped ZnO-based varistor ceramic with a diameter of 40 mm was employed to investigate the regional heterogeneity induced by cold sintering and subsequent annealing. The synergistic effects of radial pressure attenuation, liquid-phase migration, Marangoni convection, and pore evacuation accelerated densification at the edges, leading to an intensified dissolution–precipitation process. Consequently, the edge region exhibited higher densification (relative density (ρ_r) = 94.3%), smaller pore volume (V_P = 0.215 cm³·g⁻¹), and larger grains (average grain size (G_aver) = 233 nm) compared with the center part (ρ_r = 91.6%, V_P = 0.385 cm³·g⁻¹, and G_aver = 189 nm). Furthermore, the regional heterogeneity originating from the CSP extended into the annealing stage, as reflected by a reduced leakage current (J_L = 0.3 μA·cm⁻²), enhanced nonlinearity (α = 66), and a high breakdown field (E_b = 1108 V·mm⁻¹) at the edge region. The superior electrical performance is attributed to the larger interface state density (N_S = 2.9×10¹⁵ m⁻²) and higher barrier height (φ_b = 1.92 eV). This work elucidates the regional effect of cold sintering and offers theoretical insight for its industrial application.

A high voltage gradient (V_g) of ZnO-based varistor ceramics is critical for realizing miniaturized and lightweight overvoltage protection devices. However, improving V_g of ZnO-based varistor ceramics through conventional high-temperature sintering process remains a significant challenge. Here, we present a strategy to fabricate ultrahigh voltage-gradient ZnO-based varistor ceramics by combining cold sintering process/spark plasma sintering (CSP–SPS) with post-annealing process. Employing CSP–SPS, the ZnO-based varistor ceramics were initially densified at 300 °C and subsequently annealed at a low temperature of 700–900 °C. CSP–SPS technique combined with a low annealing temperature enables the production of ZnO-based varistor ceramics with fine and homogeneous microstructures, while suppressing the volatilization of Bi-rich phases at grain boundaries. This approach achieves the ultrahigh V_g of ~1832.71 V/mm, high nonlinear coefficient (α) of ~106.69, and low leakage current density (J_L) of less than 0.2 μA/cm². This work shows that the integration of CSP–SPS and post-annealing provides a promising way to design ZnO-based varistor ceramics with ultrahigh V_g.