We proposed the analytical models to analyze shifts in threshold voltage and drain induced barrier lowering (DIBL) when the stacked SiO₂/high-k dielectric was used as the oxide film of Junctionless Cylindrical Surrounding Gate (JLCSG) MOSFET. As a result of comparing the results of the presented model with those of TCAD, it was a good fit, thus proving the validity of the presented model. It could be found that the threshold voltage increased, but DIBL decreased by these models as the high-k dielectric constant increased. However, the shifts of threshold voltage and DIBL significantly decreased as the high-k dielectric constant increased. As for the degree of reduction, the channel length had a greater effect than the thickness of the high-k dielectric, and the shifts of threshold voltage and DIBL were kept almost constant when the high-k dielectric constant was 20 or higher. Therefore, the use of dielectrics such as HfO₂/ZrO₂, La₂O₃, and TiO₂ with a dielectric constant of 20 or more for stacked oxide will be advantageous in reducing the short channel effect. In conclusion, these models were able to sufficiently analyze the threshold voltage and DIBL.

An analytical SS model is presented to observe the subthreshold swing (SS) of a junctionless gate-all-around (GAA) FET with ferroelectric in this paper. For the gate structure, a multilayer structure of metal-ferroelectric-metal-insulator-semiconductor (MFMIS) was used, and the SS was calculated in $15⩽P_r⩽30\mu C/c{m}^2$ and $0.8⩽E_c⩽1.5MV/cm$, which are the ranges of remanent polarization and coercive field suggested in various experiments in the case of HZO as the ferroelectric material. It was found that the SSs from the presented analytical SS model agree well with those derived from the relationship between drain current and gate voltage using a 2D potential distribution in the range of device parameters used for simulation. As a result of analyzing the SS of the junctionless GAA FET with ferroelectric using the analytical SS model presented in this paper, the SS decreased because the voltage across the inner gate decreased when the ferroelectric thickness increased. It was observed that the condition of SS < 60 mV/dec was sufficiently obtained according to changes in device parameters such as channel length, channel radius and ferroelectric thickness, and that the SS maintained a constant value according to the ratio of remanent polarization and coercive field P_r/E_c. As P_r/E_c increases, the SS increases as the ferroelectric capacitance increases. As the channel length becomes smaller, the change in SS according to P_r/E_c is more severe.

An analytical subthreshold swing (SS) model has been presented to determine the SS of an elliptic junctionless gate-all-around field-effect transistor (GAA FET). The analysis of a GAA FET with an elliptic cross-section is essential because it is difficult to manufacture a GAA FET with an accurate circular cross-section during the process. The SS values obtained using the proposed SS model were compared with 2D simulation values and other papers to confirm good agreement. Using this analytical SS model, SS was analyzed according to the eccentricity of the elliptic cross-section structure. As a result, it was found that the carrier control ability within the channel improved as the eccentricity increased due to a decrease in the effective channel radius by a decrease in the minor axis length and a decrease in the minimum potential distribution within the channel, and thus the SS decreased. There was no significant change in SS until the eccentricity increased to 0.75 corresponding to the aspect ratio (AR), the ratio of the minor and major axis lengths, of 1.5. However, SS significantly decreased when the eccentricity increased to 0.87 corresponding to AR = 2. As a result of the SS analysis for changes in the device parameters of the GAA FET, changes in the channel length, radius, and oxide film thickness significantly affected the changing rate of SS with eccentricity.