The rapid proliferation of Internet of Things (IoT) devices necessitates lightweight cryptographic algorithms and their secure physical implementations. Masking, as a provably secure countermeasure against Side-Channel Attacks (SCA), has been extensively studied in the context of lightweight cryptography algorithms. Currently, some cryptographers have proposed a low-cost Threshold Implementation (TI) of the uBlock algorithm. However, their approach suffers from significant area overhead due to the inefficient serial and pipelined implementation of uBlock’s Pshufb-Xor (PX) network structure. To address this issue, we develop a new serial and pipelined implementation method that optimizes the area of the uBlock algorithm. Based on this optimization, we implement a 2-share TI scheme for uBlock that requires minimal area resources and does not need fresh randomness. Compared to the state-of-the-art appoach, our method reduces slice area by 63.4% on Field Programmable Gate Arrays (FPGA) platform and Gate Equivalent (GE) area by 17.2% on Application-Specific Integrated Circuit (ASIC) platform for the unprotected implementation. For the protected implementation, our method reduces slice area by 41.5% and GE area by 14.0%. Finally, our protection scheme is validated using the automated tool PROLEAD and evaluated with Test Vector Leakage Assessment (TVLA), achieving first-order glitch-extended probing security.