The Vienna rectifier is widely used in three-phase power conversion systems owing to its advantages such as high efficiency and low harmonic distortion. However, its inherent topology limits its operation exclusively to conditions in which the grid voltage and current remain in phase. When a phase difference exists between the voltage and current, notable distortions arise in the AC current, particularly around the zero-crossing points, which severely affects the power quality and system stability. Such distortion increases total harmonic distortion, introduces electromagnetic interference, and reduces rectifier reliability. Therefore, analyzing the mechanism underlying zero-crossing distortion and developing an effective suppression strategy are essential for improving the performance of Vienna rectifiers in practical applications.

To address the zero-crossing distortion problem in the Vienna rectifier, this study proposes an improved direct power control (DPC) strategy integrated with dual second-order generalized integrators (DSOGIs) for frequency and phase synchronization. The mathematical model of the Vienna rectifier in the αβ coordinate system and the conventional DPC strategy in the same coordinate system are analyzed. The cause of current zero-crossing distortion is examined from a vector perspective, revealing that the distortion primarily arises from the phase mismatch between the grid voltage and the input current during switching transitions. Specifically, the three-level topological structure of the Vienna rectifier imposes inherent constraints on current commutation, aggravating phase asynchrony as the current approaches zero and resulting in irreversible current clamping and waveform distortion. Based on this analysis, a DSOGI-based frequency-locked loop is introduced to accurately track the grid frequency and a DSOGI-based phase-locked loop (PLL) is employed to lock the current phase. The phase adjustment is implemented through the real-time modification of the reference voltage vector in the DPC strategy, in which the phase information obtained from the DSOGI-PLL dynamically corrects the reference voltage angle, ensuring that the input current follows the grid voltage phase with high fidelity. By adjusting the phase relationship between the output voltage and current, the proposed method maintains in-phase operation, thereby reducing the distortion region around the current zero-crossing points. Voltage and current vector diagrams of the Vienna rectifier before and after the improvement are presented, along with the control block diagram of the current zero-crossing distortion suppression strategy for the DPC of the Vienna rectifier.

The proposed DPC-based zero-crossing distortion suppression strategy is validated through detailed simulation studies. The results demonstrate that the method markedly reduces current distortion near the zero-crossing points. The output current quality is considerably enhanced, with a reduction in harmonic components and a more sinusoidal current waveform.

The simulation results verify the effectiveness and robustness of the proposed method, demonstrating its potential for enhancing the performance of Vienna rectifiers in practical power conversion systems. This strategy provides a feasible solution for suppressing zero-crossing distortion while preserving the advantages of traditional DPC, offering valuable insights for further research and application in high-performance rectifier designs.

The Vienna rectifier, evolved from the T-type three-level inverter, offers a simple structure, few power devices, and no dead zone effect. These advantages not only reduce output voltage distortions and simplify control strategies but also mitigate switching losses of power devices. The Vienna rectifier has become one of the most well-known rectifier topologies and is widely applicable in electric vehicle fast charging stations, renewable energy grid integration, and high-performance power factor correction systems. However, the Vienna rectifier can only operate under the condition where the alternating current (AC) and AC voltage of the rectifier have the same phase; otherwise, serious current zero-crossing distortion problems will occur. Because of sampling delays and the influence of grid-side three-phase filters, there exists a phase difference between the AC voltage and current of the rectifier, leading to significant distortions at three-phase current zero-crossing points. Given that the filter parameters of the Vienna rectifier are nonlinear and affected by several factors, such as current frequencies and temperature, accurate values are difficult to obtain. Consequently, the effectiveness of existing strategies for current zero-crossing minimization with filter parameters will be impaired by inaccurate parameters.

Therefore, in this study, the factors causing current zero-crossing distortions are analyzed from the perspective of current flow paths and vector graphics with the conventional dual closed-loop control strategy. Based on the analysis, a current zero-crossing distortion minimization strategy without filter parameters for the Vienna rectifier is proposed. A double second-order general integrator phase-locked loop (DSOGI-PLL) is adopted to extract the phases of the grid and rectifier AC voltages, and the phase difference caused by the L or LCL filter is accurately obtained. The reactive current command is first calculated using the integration of DSOGI-PLL and then set as the q-axis current reference. The reactive current compensation is subsequently implemented using a cascaded control structure composed of outer voltage stabilization and inner current tracking loops. With a dual closed-loop control strategy, the Vienna rectifier AC voltages and the grid-connected currents are synchronized, thereby suppressing current zero-crossing distortions.

Simulation models in MATLAB/Simulink are built for Vienna rectifiers with L and LCL filters. In the simulation results, the output current is severely distorted when the conventional dual closed-loop control strategy is employed without the reactive current compensation, and the total harmonic distortions (THDs) of the currents with L filters are 1.52%, 1.53%, and 1.49%. With the proposed current zero-crossing distortion minimization strategy, the distortions of the three-phase currents are significantly reduced, and the harmonic distortions have been significantly attenuated. The corresponding THDs of the three-phase currents are all 1.26%. At the same time, the proposed strategy is also effective with LCL filters. With the conventional dual closed-loop control strategy, the THDs of the three-phase currents with LCL filters are all 1.11%. After the proposed current zero-crossing distortion minimization strategy is employed, the THDs of the three-phase currents with LCL filters are 1.01%, 0.98%, and 0.99%. The current zero-crossing distortions are also effectively suppressed.

The theoretical analysis and simulation results verified that the proposed control strategy for the Vienna rectifier can effectively minimize current zero-crossing distortions without filter parameters.

Current source inverter (CSI) is a highly promising power electronic converter. Because of its large inductance connected in series on the DC side, the CSI exhibits a boost characteristic. Moreover, its power circuit can endure a short shoot-through state, providing relatively high reliability. At present, CSI is applied in fields such as photovoltaic power generation and high-power motor drives and is an important equipment for electrical energy conversion. Many characteristics of CSI include duality attributes with the voltage source inverter (VSI). To prevent shoot-through failure, a dead time must be added between complementary drive signals in the VSI. Correspondingly, in the CSI, an overlap region between the complementary drive pulses must be added to provide a freewheeling path. The overlap-time effect of CSI is similar to the dead-time effect of the VSI, which can also increase the output current harmonics. The overlap-time effect must be compensated to improve the quality of output power. Meanwhile, conventional space vector pulse-width modulation (SVPWM) requires a series of complex steps, such as sector determination, time calculation, and allocation. Simplified SVPWM can be applied in VSI to reduce the computational complexity. However, there is limited research on simplified SVPWM for three-phase CSI. If the overlap-time compensation strategy is implemented using conventional SVPWM, the implementation process becomes complex and computationally intensive.

Therefore, in this paper, the conventional SVPWM implementation method is analyzed for three-phase CSI. Accordingly, a simplified SVPWM for generating saddle-shaped modulation waves is proposed, which can avoid a series of complex steps. Furthermore, the current deviation vector generated by the overlap-time effect is analyzed. A simplified overlap-time compensation strategy based on SVPWM is proposed.

A three-phase CSI simulation model was built in MATLAB/Simulink to verify the proposed simplified overlap-time compensation strategy based on SVPWM. The overlapping area times were set to 3 and 5 μs, respectively. The proposed simplified overlap-time compensation strategy based on SVPWM is enabled at 0.04 s. The output current waveforms before and after the overlap-time compensation are analyzed and compared. The fast Fourier transform results of output currents are presented. As can be seen from the results in this paper, the output current is severely distorted before compensation, and the total harmonic distortions (THDs) of the currents with 3- and 5-μs overlap times are 4.25% and 7.48%, respectively. After the overlap-time compensation, the distortions of the output currents were significantly reduced, and the corresponding THDs were 1.49% and 1.35%, respectively. At the same time, the 5^th, 7^th, 11^th, and 13^th harmonics in output currents are significantly reduced.

Using theoretical analysis and simulation results, this study proved that the proposed simplified overlap-time compensation strategy based on SVPWM can effectively reduce the impact of the overlap time and improve the quality of output currents. Moreover, the proposed method can effectively simplify the implementation process and reduce the computational complexity of the overlap-time compensation strategy.