This study aims to improve the operation efficiency of autonomous intelligent collaborative harvesting using multiple unmanned harvesters and unmanned grain transport vehicles over multiple plots. A task planning was proposed to optimize using a chaotic adaptive nonlinear particle swarm algorithm in the field of intelligent agricultural machinery. A task planning model was then established to reduce the total operation time and total energy consumption of agricultural machinery. Two operation modes were provided for the multi-machine collaborative harvesting. Among them, one mode was the “n:n” harvesting and transportation, and another was the “n:(n-1)” harvesting and transportation, where n=3. Three harvesters and three grain transport vehicles were evenly distributed in the three large fields. Once the harvester arrived at the unloading point, the grain transport vehicle received the signal and then departed from the garage to the unloading point. Furthermore, the unloading operation was only performed at the field edge. In mode 2, the 3 harvesters and 2 grain transport vehicles were configured to allocate into 3 fields for the collaborative operations using the CANPSO algorithm. The transport vehicles followed the harvesters into the waiting area at the field entrance/exit. Once receiving the unloading signal, the vehicles were transported from the waiting area to the unloading point. At the same time, the unloading operation was performed at random locations in the field. The travel paths of the grain transport vehicles were limited only to the post-harvested areas, rather than traversing the unharvested areas. Simulation results indicated that the CANPSO algorithm was more efficient for global optimization of the multi-machine cooperative harvesting. Compared with the conventional PSO algorithm, the CANPSO was reduced by 14.27% and 13.44%, respectively, in terms of the total operation time and total energy consumption of the agricultural machinery. The superior performance of the algorithm was verified after optimization. Platform test results indicated that the 3:2 collection and transportation collaborative operation performed better in the task planning. The PSO, CANPSO algorithms, and different collection and transportation modes were deployed on the self-developed swarm collaboration and cognitive computing platform. The 3:2 collection and transportation mode reduced the total operation time by 11.80% and the total energy consumption of agricultural machinery by 19.31%, compared with the conventional PSO framework. The superior performance was verified in the 3:2 collection and transportation mode. Furthermore, the CANPSO algorithm reduced the total operation time by 19.56% and the total energy consumption of agricultural machinery by 10.09%, compared with the PSO algorithm. The harvesting efficiency was improved under the 3:2 collection and transportation mode. The field trial test indicated that the task planning of multi-machine autonomous intelligent collaborative harvesting was achieved in wheat harvesting and transportation. Three harvesters and two grain transport vehicles were involved to enhance the fault tolerance of the field trial. The time and energy consumption were balanced for the majority of daily harvesting. The operational efficiency of the 3:2 transport mode optimized by CANPSO was improved by 21.11% and 20.53%, respectively, compared with the 3:3 and 3:2 transport modes optimized by PSO under the balanced weighting. The ratio of harvesters to grain transport vehicles was adjusted according to the requirements of the actual operation. Additionally, the task planning was extended to a similar crop harvesting. The finding can provide data support for the large-scale field application of the task planning.

This paper introduces a $\mathrm{\Delta }-\mathrm{\Sigma }$ fractional output divider (FOD) designed for audio system-on-chip (SoC) applications with low design and implementation cost. In contrast to conventional FOD design methodologies that utilize a multi-modulus divider (MMD) or a multi-phase multiplexer (MPM) based divider incorporating complex jitter filters, the proposed FOD adopts a feed-forward architecture employing simple circuit building blocks. It leverages a $\mathrm{\Delta }-\mathrm{\Sigma }$ digital-to-frequency converter (DFC) to generate fractionally synthesized output frequencies, eliminating the synchronous constraint associated with MMD and MPM methods. The DFC employs a fully-synthesizable $\mathrm{\Delta }-\mathrm{\Sigma }$ modulator and resistor-2 resistor (R-2R) digital-to-analog converter to generate 4-level waveform patterns containing the desired output frequency information. These patterns are then processed through an integrator and a zero-crossing detector to reconstruct the fractionally divided output clock signal. Furthermore, to minimize jitter, a simple edge combiner-based jitter filter is cascaded with the DFC output. Implemented in 180 nm digital complementary metal-oxide-semiconductor process and operating at 1.2 V supply voltage, the proposed FOD offers an output frequency range of 500 kHz to 45 MHz, with $N_{\mathrm{m}\mathrm{i}\mathrm{n}}=F_{\mathrm{I}\mathrm{N}}/F_{\mathrm{O}\mathrm{U}\mathrm{T}}=4$. Specifically, It divides a 26 MHz input to generate a 6.144 MHz (128fs = 128 × 44.1 kHz) output, exhibiting a root-mean-square jitter of 3.68 ps, while consuming 0.22 mW of power.

This paper presents a dual-function circuit for system-on-chip (SoC) applications that integrates both a temperature sensor and a voltage-monitoring analog-to-digital converter (ADC) within a single architecture. Unlike conventional bipolar junction transistor (BJT) based sensor implementations, which require multiple precisely matched BJTs, operating voltages higher than 1 V, dedicated ADCs, and complex signal-conditioning networks, the proposed design employs a single BJT as the sole sensing element and a simple ΔΣ switched-capacitor modulator, thereby reducing both area and design complexity. Fabricated in a 180 nm CMOS process, the proposed circuit operates at 0.95 V, consumes 890 nW, and occupies 0.0087 mm². As a temperature sensor, it achieves an accuracy of ±1.8^◦C (3σ) over a range of -30^◦C to 120^◦C after one-point trimming at 30^◦C. As a voltage-monitoring ADC, it delivers an 11-bit resolution with ±0.046% accuracy over a 0 to 5 V input range. These characteristics make the proposed circuit highly suitable for real-time thermal and voltage monitoring in power- and area-constrained SoCs, Moreover, by combining both temperature and voltage monitoring ADC in a single compact architecture, the proposed design significantly reduces system costs and complexity.