Disk failures, the most common and major failures in storage systems, increase the risk of service interruption and data loss, and bring additional maintenance costs, which reduces system reliability. Disk failure prediction methods aim to forecast failures, initiating prompt data migration and disk replacement. Existing methods continuously optimize the models with different sampling methods and modeling algorithms. However, due to issues such as inaccurate sample labeling, insufficient data sampling, and improper sample segmentation, the predictive capabilities of existing models within the lookahead-window time are unstable and decline as the lookahead-window time increases. To address this, we propose LWCM (Lookahead-Window Constrained Model) to improve the predictability and stability of failure prediction models within the lookahead-window time. LWCM leverages dynamic sample relabeling methods based on lookahead-window time constraints and failure symptom durations to modify inaccurate sample labels. LWCM utilizes effective sample data by using the two-phase data sampling method including initial expectation sampling and subsequent segmented resampling. LWCM employs dynamic weighted optimization in backpropagation to enhance the predictability and stability of the disk failure prediction model. Experimental results show that LWCM has better failure prediction performance. The true positive and false positive rates surpass those of the offline-RF model by 38.7% and 92.4%, respectively. Furthermore, LWCM demonstrates its applicability across disk models while maintaining stability within the lookahead constraint window.

Resistive random access memory (RRAM) enables the functionality of operating massively parallel dot products and accumulations. RRAM-based accelerator is such an effective approach to bridging the gap between Internet of Things devices’ constrained resources and deep neural networks’ tremendous cost. Due to the huge overhead of Analog to Digital (A/D) and digital accumulations, analog RRAM buffer is introduced to extend the processing in analog and in approximation. Although analog RRAM buffer offers potential solutions to A/D conversion issues, the energy consumption is still challenging in resource-constrained environments, especially with enormous intermediate data volume. Besides, critical concerns over endurance must also be resolved before the RRAM buffer could be frequently used in reality for DNN inference tasks. Then we propose LayCO, a layer-centric co-optimizing scheme to address the energy and endurance concerns altogether while strictly providing an inference accuracy guarantee. LayCO relies on two key ideas: 1) co-optimizing with reduced supply voltage and reduced bit-width of accelerator architectures to increase the DNN’s error tolerance and achieve the accelerator’s energy efficiency, and 2) efficiently mapping and swapping individual DNN data to a corresponding RRAM partition in a way that meets the endurance requirements. The evaluation with representative DNN models demonstrates that LayCO outperforms the baseline RRAM buffer based accelerator by 27x improvement in energy efficiency (over TIMELY-like configuration), 308x in lifetime prolongation and 6x in area reduction (over RAQ) while maintaining the DNN accuracy loss less than 1%.