Flexible printed circuit (FPC) design in complex scenarios has a list of pin concentration areas, which lead to extremely congested intersection regions while connecting the pins. Currently, it is challenging to explore the routability and to find topologically non-crossing and routable paths manually for the nets timely. The existing bus planning methods cannot offer optimal solutions concerning the special resource distribution of the FPC design. To investigate an effective way to shorten the routing time of FPC and achieve enhanced performance, a bus planning algorithm is proposed to tackle complex area connection problems. On the basis of the pin location information, the routing space is partitioned and generally represented as an undirected graph, and the topological non-crossing relationship between different regions is obtained using the dynamic pin sequence. Considering the routability and electrical constraints, a heuristic algorithm is proposed to search the optimal location of the crossing point on the region boundary. Experimental results on industrial cases show that the proposed algorithm realize better performance in terms of count and routability in comparison with numerous selected state-of-the-art router and methods.

Integrated circuit (IC) camouflaging technique has been applied as a countermeasure against reverse engineering (RE). However, its effectiveness is threatened by a boolean satisfiability (SAT) based de-camouflaging attack, which is able to restore the camouflaged circuit within only minutes. As a defense to the SAT-based de-camouflaging attack, a brand new camouflaging strategy (called CamoPerturb) has been proposed recently, which perturbs one minterm by changing one gate’s functionality and then restores the perturbed circuit with a separated camouflaged block, achieving good resistance against the SAT-based attack. In this paper, we analyze the security vulnerabilities of CamoPerturb by illustrating the mechanism of minterm perturbation induced by gate replacement, then propose an attack to restore the changed gate’s functionality, and recover the camouflaged circuit. The attack algorithm is facilitated by sensitization and implication principles in automatic test pattern generation (ATPG) techniques. Experimental results demonstrate that our method is able to restore the camouflaged circuits with very little time consumption.