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Design and application of a logic synthesis tool development framework
Experimental Technology and Management 2025, 42(2): 152-161
Published: 20 February 2025
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[Objective]

The proliferation of specialized demonstrative software colleges has highlighted the growing importance of focusing on the development of large-scale industrial software, particularly in the domain of electronic design automation (EDA) tools. EDA tools are pivotal in chip design, with logic synthesis tools being a critical component within this ecosystem. Despite the increasing emphasis on EDA tools in educational curricula, current courses tend to concentrate on the application of these tools rather than delving into the practical development of logic synthesis tools. This education gap can hinder the cultivation of a new generation of engineers equipped with the skills necessary to innovate in this field. To address this issue, this study aims to bridge the educational divide by introducing a scaffolding-based teaching approach that encompasses the design and implementation of a logic synthesis tool development framework, LoSTDeF, complete with accompanying experimental content and datasets. The aim is to provide students with a deep understanding of hardware design optimization processes and to enhance their practical capabilities in the field of EDA tool development.

[Methods]

The methodology employed in this study involved the design and implementation of the LoSTDeF framework, which was grounded in scaffolding-based teaching principles. This approach was designed to gradually guide students through the complexities of logic synthesis tool development. The framework included a comprehensive set of experimental content and datasets that were carefully curated to facilitate a progressive learning experience. The experimental content was structured to start with fundamental concepts and gradually increase in complexity, allowing students to build a solid foundation before tackling more advanced topics. The datasets provided were real-world scenarios that students must apply their knowledge to, ensuring that the learning was relevant and applicable to industry standards. The teaching approach also involved interactive sessions, where students can engage with the material, ask questions, and receive immediate feedback, fostering a dynamic learning environment.

[Results]

The innovative results of this study were manifold. First, the LoSTDeF framework was successfully implemented, providing a robust platform for students to learn and practice logic synthesis tool development. The framework’s effectiveness was evidenced by the enhanced understanding of logic synthesis-related knowledge and algorithms demonstrated by the students. Second, the practical skills of the students were significantly improved as they were able to apply theoretical concepts to real-world problems through the use of experimental content and datasets. The teaching practice showed that students not only gained a deeper comprehension of the subject matter but also became proficient in the practical aspects of EDA tool development. This was further validated by the positive feedback from students and the observable improvement in their ability to tackle complex design challenges.

[Conclusions]

In conclusion, the study successfully demonstrated the importance and necessity of integrating practical development experiences into the education of EDA tools, particularly in the realm of logic synthesis. The LoSTDeF framework, developed as part of this research, proved to be an effective tool for enhancing students’ understanding and practical skills in this area. The results indicated that a scaffolding-based teaching approach, combined with a well-designed experimental curriculum, significantly improved educational outcomes. This study contributes to the field of engineering education by providing a model for developing practical, industry-relevant curricula that prepare students for the challenges of modern chip design and EDA tool development. The success of LoSTDeF underscores the potential for similar frameworks to be applied in other areas of engineering, offering a scalable solution for enhancing educational experiences and outcomes.

Regular Paper Issue
Improved Task and Resource Partitioning Under the Resource-Oriented Partitioned Scheduling
Journal of Computer Science and Technology 2019, 34(4): 839-853
Published: 19 July 2019
Abstract Collect

Coordinated partitioning and resource sharing have attracted considerable research interest in the field of real-time multiprocessor systems. However, finding an optimal partition is widely known as NP-hard, even for independent tasks. A recently proposed resource-oriented partitioned (ROP) fixed-priority scheduling that partitions tasks and shared resources respectively has been shown to achieve a non-trivial speedup factor guarantee, which promotes the research of coordinated scheduling to a new level. Despite the theoretical elegance, the schedulability performance of ROP scheduling is restricted by the heuristic partitioning methods used in the original study. In this paper, we address the partitioning problem for tasks and shared resources under the ROP scheduling. A unified schedulability analysis framework for the ROP scheduling is proposed in the first place. A sophisticated partitioning approach based on integer linear programming (ILP) is then proposed based on the unified analysis. Empirical results show that the proposed methods improve the schedulability of ROP scheduling significantly, and the runtime complexity for searching a solution is reduced prominently compared with other ILP-based approaches as well.

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