Fully homomorphic encryption (FHE) enables computation over encrypted data without decryption, ensuring data confidentiality throughout the processing pipeline. However, the complexity and heterogeneity of FHE schemes like CKKS, BFV, and TFHE pose challenges for unified hardware design. In this paper, we propose the Homomorphic Processing Unit (HPU), a general-purpose platform supporting multiple FHE schemes. Unlike fixed-function accelerators, HPU is implemented as a RISC-V extension and introduces a dedicated homomorphic instruction set architecture (H-ISA), comprising micro-instructions for minimal compute kernels and macro-instructions for integration with general-purpose models. Core operations like the number-theoretic transform (NTT) and automorphism are abstracted into a unified instruction layer, mapped onto specialized homomorphic compute units. HPU integrates a collaborative computation and storage design, utilizing a polynomial-level instruction set and a polynomial-granular memory management unit (MMU) to optimize memory and reduce data movement. By combining a complete ISA with a general-purpose computing core, HPU can achieve efficient computing, control, and scheduling. We evaluate the HPU prototype using four multi-FHE benchmarks on field-programmable gate array (FPGA) and 7 nm ASIC. The key results are as follows. 1) HPU achieves up to 1596x and 1174x speedup over CPU for CKKS-like and TFHE operations, respectively. 2) Compared with SOTA FPGA solutions for CKKS and TFHE, HPU achieves 1.36x and 1.2x improvement, respectively. 3) HPU's ASIC implementation achieves 1.36x speedup over state-of-the-art TFHE accelerators for long short-term memory (LSTM).

As conventional CPU-based security architectures struggle to scale with ever-growing network bandwidths and increasingly sophisticated cyberattacks, the data processing unit (DPU), a specialized processor for datacenter infrastructure, has emerged as a transformative foundation for secure and high-performance computing. Unlike prior fragmented studies, this work proposes a comprehensive security framework for DPUs by systematically investigating the DPUs' dual role in cybersecurity, serving both as an active security enforcer and as a critical component that must itself be protected. First, the framework offloads security policies onto the DPU to enable line-rate packet inspection and hardware-accelerated security processing. Second, the framework re-architects the DPU itself to defend against physical and architectural attacks, acknowledging that the DPU also introduces a new attack surface. We validate these two design directions through two representative case studies, demonstrating the effectiveness and practicality of the proposed DPU security framework. Experimental results show that the proposed framework reduces remote direct memory access (RDMA) cache side-channel detection latency by up to 98.7% compared with the state-of-the-art, while enabling a trusted execution environment on field-programmable gate array (FPGA)-based DPUs with sub-100 ns overhead and less than 4% FPGA resource consumption.

Mining from simulation data of the golden model in hardware design verification is an effective solution to assertion generation. While the simulation data is inherently incomplete, it is necessary to evaluate the truth values of the mined assertions. This paper presents an approach to evaluating and constraining hardware assertions with absent scenarios. A Belief-failRate metric is proposed to predict the truth/falseness of generated assertions. By considering both the occurrences of free variable assignments and the conflicts of absent scenarios, we use the metric to sort true assertions in higher ranking and false assertions in lower ranking. Our Belief-failRate guided assertion constraining method leverages the quality of generated assertions. The experimental results show that the Belief-failRate framework performs better than the existing methods. In addition, the assertion evaluating and constraining procedure can find more assertions that cover new design functionality in comparison with the previous methods.

Circular self test path (CSTP) is an attractive technique for testing digital integrated circuits(IC) in the nanometer era, because it can easily provide at-speed test with small test data volume and short test application time. However, CSTP cannot reliably attain high fault coverage because of difficulty of testing random-pattern-resistant faults. This paper presents a deterministic CSTP (DCSTP) structure that consists of a DCSTP chain and jumping logic, to attain high fault coverage with low area overhead. Experimental results on ISCAS’89 benchmarks show that 100% fault coverage can be obtained with low area overhead and CPU time, especially for large circuits.

In wireless sensor networks (WSNs), a faulty sensor may produce incorrect data and transmit them to the other sensors. This would consume the limited energy and bandwidth of WSNs. Furthermore, the base station may make inappropriate decisions when it receives the incorrect data sent by the faulty sensors. To solve these problems, this paper develops an online distributed algorithm to detect such faults by exploring the weighted majority vote scheme. Considering the spatial correlations in WSNs, a faulty sensor can diagnose itself through utilizing the spatial and time information provided by its neighbor sensors. Simulation results show that even when as many as 30% of the sensors are faulty, over 95% of faults can be correctly detected with our algorithm. These results indicate that the proposed algorithm has excellent performance in detecting fault of sensor measurements in WSNs.