Virtualization improves physical hardware utilization of cloud computing by over-committing hardware in the virtual machine. However, applications running in virtual machines suffer significant performance degradation as they do not take advantage of the features of physical hardware, which cannot be overcome by optimization of the virtual hardware. In order to reduce this performance overhead, an application virtualization mechanism is proposed to expose application instances running in the host operation system to the virtual machine, so the virtual machine can achieve optimal performance by using host instances on the real hardware. A virtio-based implementation named virtio-vapp is also proposed to show the needed adaptions. The virtio-vapp is evaluated against other communication components in Qemu to show the high load capacity and low latency of virtio-vapp. In the evaluation, virtio-vapp has a bandwidth of 36.4 Gbit/s in experiments, which is almost the same performance as the host. In addition to high load capacity and low latency, virtio-vapp supports limited migration to allow virtual machines to run applications with the same data. These results show that application virtualization can significantly reduce the performance overhead and improves flexibility and usability compared to running applications directly in the virtual machine.

Floorplan is an important process whose quality determines the timing closure in integrated circuit (IC) physical design. And generating a floorplan with satisfying timing result is time-consuming because much time is spent on the generation-evaluation iteration. Applying machine learning to the floorplan stage is a potential method to accelerate the floorplan iteration. However, there exist two challenges which are selecting proper features and achieving a satisfying model accuracy. In this paper, we propose a machine learning framework for floorplan acceleration with feature selection and model stacking to cope with the challenges, targeting to reduce time and effort in integrated circuit physical design. Specifically, the proposed framework supports predicting post-route slack of static random-access memory (SRAM) in the early floorplan stage. Firstly, we introduce a feature selection method to rank and select important features. Considering both feature importance and model accuracy, we reduce the number of features from 27 to 15 (44% reduction), which can simplify the dataset and help educate novice designers. Then, we build a stacking model by combining different kinds of models to improve accuracy. In 28 nm technology, we achieve the mean absolute error of slacks less than 23.03 ps and effectively accelerate the floorplan process by reducing evaluation time from 8 hours to less than 60 seconds. Based on our proposed framework, we can do design space exploration for thousands of locations of SRAM instances in few seconds, much more quickly than the traditional approach. In practical application, we improve the slacks of SRAMs more than 75.5 ps (177% improvement) on average than the initial design.